• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.07a
• /
• pp.280-283
• /
• 2004

This paper discribes the design concept, fabrication process and measuring result of 2.5kV Gate Commutated Thyristor devices. Integrated gate commutated thyristors(IGCTs) is the new power semiconductor device used for high power inverter, converter, static var compensator(SVC) etc. Most of the ordinary GTOs(gate turn-off thyristors) are designed as non-punch-through(NPT) concept; i.e. the electric field is reduced to zero within the N-base region. In this paper, we propose transparent anode structure for fast turn-off characteristics. And also, to reach high breakdown voltage, we used 2-stage bevel structure. Bevel angle is very important for high power devices, such as thyristor structure devices. For cathode topology, we designed 430 cathode fingers. Each finger has designed $200{\mu}m$ width and $2600{\mu}m$ length. The breakdown voltage between cathode and anode contact of this fabricated GCT device is 2,715V.

• Proceedings of the KIPE Conference
• /
• 2014.07a
• /
• pp.367-368
• /
• 2014

This paper investigates characteristics of high power semiconductor device losses in 5MW-class Permanent Magnet Synchronous Generator (PMSG) Medium Voltage (MV) wind turbines. High power semiconductor device of press-pack type IGCT of 6.5kV is considered in this paper. Analysis is performed based on neutral point clamped (NPC) 3-level back-to-back type voltage source converter (VSC) supplied from grid voltage of 4160V. This paper describes total loss distribution at worst case under inverter and rectifier operating mode for the power semiconductor switches. The loss analysis is confirmed through PLECS simulations. In addition, the loss factors due to di/dt snubber and ac input filter are presented. The investigation result shows that IGCT type semiconductor devices generate the total efficiency of 97.74% under the rated condition.

• Journal of Power Electronics
• /
• v.10 no.6
• /
• pp.643-646
• /
• 2010

An interactive web-based teaching tool for a power semiconductor course at the University of Central Florida is presented in this paper. A novel approach is introduced using Technology Aided Design Tools (TCAD) to generate time-lapsed 2D semiconductor device cross-section embedded in a webpage using $Adobe^{(R)}$ Flash (web design tool) platform to create interactive movies that demonstrate complex device physical phenomenon. Students can step through the interactive movies forward, backward, pausing, or looping. Each step represents a giving bias condition. Current-voltage plots are represented along with the semiconductor device and a visual point is placed on the IV curve to indicate the current bias conditions. The changes are then reflected in the 2D cross-section movie area and the IV plot. This tool was implemented in a classroom setting to augment the lectures or for discovery learning.

• Journal of the Microelectronics and Packaging Society
• /
• v.21 no.2
• /
• pp.13-21
• /
• 2014

Technology for high power devices has made impressive progress in increasing the current density of power semiconductor, system module, and design optimization, which realize high power systems with heterogeneous functional integration. Depending on the performance development of high power semiconductor, packaging technology of high power device is urgently required for efficiency improvement of the device. Power device packaging must provide superior thermal management due to high operating temperature of power modules. Here we, therefore, review critical challenges of typical power electronics packaging today including core assembly processes, component materials, and reliability evaluation regulations.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.25 no.3
• /
• pp.165-169
• /
• 2012

Power semiconductor devices are widely used as high voltage applications to inverters and motor drivers, etc. The blocking voltage is one of the most important parameters for power semiconductor devices. And cause of junction curvature effects, the breakdown voltage of the device edge and device unit cells was found to be lower than the 'ideal' breakdown voltage limited by the semi-infinite junction profile. In this paper, Propose the methods for field ring design by DOE (Design of Experimentation). So The field ring can be improve for breakdown voltage and optimization.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2006.08a
• /
• pp.556-559
• /
• 2006

We successfully developed a high performance and highly reliable blazed GxL device with a high optical efficiency and a high contrast ratio. The device demonstrated superior resistance against a high power laser, which is suitable for a large-area laser projector. We operated the world's largest laser projection screen using this device at the 2005 World Exposition in Aichi, Japan, problem free.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.11a
• /
• pp.3-6
• /
• 2004

Power semiconductor devices are being compact, high performance and intelligent thanks to recent remarkable developments of silicon design, process and related packaging technologies. Developments of MOS-gate transistors such as MOSFET and IGBT are dominant thanks to their advantages on high speed operation. In conjunction with package technology, silicon technologies such as trench, charge balance and NPT will support future power semiconductors. In addition, wide band gap material such as SiC and GaN are being studies for next generation power semiconductor devices.

• Proceedings of the KIEE Conference
• /
• 2002.07c
• /
• pp.1578-1580
• /
• 2002

The breakdown and on-state characteristics of the multi-RESURF SOI LDMOSFET is presented. P-/n-epi layer thickness and doping concentration is varied from $2{\mu}m{\sim}5{\mu}m$ and $1{\times}10^{15}/cm^3{\sim}9{\times}10^{15}/cm^3$ to obtain optimum breakdown voltage and on-resistance. The breakdown and on-state characteristics of the device is verified by two-dimensional process simulator ATHENA and device simulator ATLAS.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.12 no.4
• /
• pp.377-387
• /
• 2012

An intrinsic small signal equivalent circuit model of Cylindrical/Surrounded gate MOSFET is proposed. Admittance parameters of the device are extracted from circuit analysis and intrinsic circuit elements are presented in terms of real and imaginary parts of the admittance parameters. S parameters are then evaluated and justified with the simulated data extracted from 3D device simulation.

• Fire Science and Engineering
• /
• v.10 no.2
• /
• pp.28-39
• /
• 1996

A recently developed electro-thermal simulation methodology is used to analyze the behavior of a PWM(Pulse-Width-Modulated) voltage source inverter which uses IGBT(Insulated Gate Bipolar Transistor) as the switching devices. In the electro-thermal network simulation methdology, the simulator solves for the temperature distribution within the power semiconductor devices(IGBT electro-thermal model), control logic circuitry, the IGBT gate drivers, the thermal network component models for the power silicon chips, package, and heat sinks as well as the current and voltage within the electrical network. The thermal network describes the flow of heat form the chip surface through the package and heat sink and thus determines the evolution of the chip surface temperature used by the power semiconductor device models. The thermal component model for the device silicon chip, packages, and heat sink are developed by discretizing the nonlinear heat diffusion equation and are represented in component from so that the thermal component models for various package and heat sink can be readily connected to on another to form the thermal network.