• ETRI Journal
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• v.43 no.4
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• pp.650-659
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• 2021

Multi-carrier waveforms have several advantages over single-carrier waveforms for radar communication. Employing multi-carrier complementary phase-coded (MCPC) waveforms in radar applications has recently attracted significant attention. MCPC radar signals take advantage of orthogonal frequency division multiplexing properties, and several authors have explored the use of MCPC signals and the difficulties associated with their implementation. The sidelobe level and peak-to-mean-envelope-power ratio (PMEPR) are the key issues that must be addressed to improve the performance of radar signals. We propose a scheme that applies pattern-based scaling and geometric progression methods to enhance sidelobe and PMEPR levels in MCPC radar signals. Numerical results demonstrate the improvement of sidelobe and PMEPR levels in the proposed scheme. Additionally, autocorrelations are obtained and analyzed by applying the proposed scheme in extensive simulation experiments.

• Nuclear Engineering and Technology
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• v.55 no.11
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• pp.4228-4237
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• 2023

The Improved Deterministic Truncation of Monte Carlo (iDTMC) is a powerful acceleration and variance reduction scheme in the Monte Carlo analysis. The concept of the iDTMC method and correlated sampling-based real variance estimation are briefly introduced. Moreover, the application of the iterative scheme to the correlated sampling is discussed. The iDTMC method is utilized in a 3-dimensional small modular reactor (SMR) model problem. The real variances of burnup-dependent criticality and power distribution are evaluated and compared with the ones obtained from 30 independent iDTMC calculations. The impact of the inactive cycles on the correlated sampling is also evaluated to investigate the consistency of the correlated sample scheme. In addition, numerical performances and sensitivity analysis on the real variance estimation are performed in view of the figure of merit of the iDTMC method. The numerical results show that the correlated sampling accurately estimates the real variances with high computational efficiencies.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.6
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• pp.2398-2421
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• 2020

In third world countries like Pakistan, the production of electricity has been quickly reduced in past years due to rely on the fossil fuel. According to a survey conducted in 2017, the overall electrical energy capacity was 22,797MW, since the electrical grids have gone too old, therefore the efficiency of grids, goes down to nearly 17000MW. Significant addition of fossil fuel, hydro and nuclear is 64.2%, 29% and 5.8% respectively in the total electricity production in Pakistan. In 2018, the demand crossed 20,223MW, compared to peak generation of 15,400 to 15,700MW as by the Ministry of Water and Power. Country faces a deficit of almost 4000MW to 5000MW for the duration of 2019 hot summer term. Focus on one aspect considering Demand Side Management (DSM) cannot oversea the reduction of gap between power demand and customer supply, which eventually leads to the issue of load shedding. Hence, a scheduling scheme is proposed in this paper called RPSMDSM that is based on selection of those appliances that need to be only Turned-On, on priority during peak hours consuming minimum energy. The Home Energy Management (HEM) system is integrated between consumer and utility and bidirectional flow is presented in the scheme. During peak hours of electricity, the RPSMDSM is capable to persuade less power consumption and accomplish productivity in load management. Simulations show that RPSMDSM scheme helps in scheduling the electricity loads from peak price to off-peak price hours. As a result, minimization in electricity cost as well as (Peak-to-Average Ratio) PAR are accomplished with sensible waiting time.

• Journal of information and communication convergence engineering
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• v.9 no.3
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• pp.301-304
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• 2011

This paper describes the possibility of a low-power, high-resolution fingerprint sensor chip. A modified capacitive detection circuit of charge sharing scheme is proposed, which reduces the static power dissipation and increases the voltage difference between a ridge and valley more than conventional circuit. The detection circuit is designed and simulated in 3.3V, 0.35${\mu}$m standard CMOS process, 40MHz condition. The result shows about 27% power dissipation reduction and 90% improvement of difference between a ridge and valley sensing voltage. The proposed circuit is more stable and effective than a typical circuit.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.692-695
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• 2011

This paper describes the possibility of a low-power, high-resolution fingerprint sensor chip. A modified capacitive detection circuit of charge sharing scheme is proposed, which reduces the static power dissipation and increases the voltage difference between a ridge and valley more than conventional circuit. The detection circuit is designed and simulated in 3.3V, $0.35{\mu}m$ standard CMOS process, 40MHz condition. The result shows about 35% power dissipation reduction and 90% improvement of difference between a ridge and valley sensing voltage. The proposed circuit is more stable and effective than a typical circuit.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.701-708
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• 1998

This paper presents a novel non-resonant PWM DC-DC converter for X-ray high-voltage power generator using the parasitic impedances of the high-voltage high-frequency link transformer with its output high-voltage control scheme and steady-state characteristics compared to the conventional series-parallel resonant DC-DC converter. The key point of this approach is to evaluate effectiveness of reduction of the turn ratio of the high-voltage high-frequency transformer on improvements in power conversion efficiency and the power factor applying a boost AC-DC converter as DC voltage source, especially in the long exposure term and light output load ranges.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.10 s.101
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• pp.995-1002
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• 2005

An orthogonal frequency division multiplexing(OFDM) system has the problem of the peak-to-average power ratio(PAR). In general, in order to obtain optimal PAR reduction using the partial transmitted sequence(PTS), the total search for the number of sub-blocks and the rotation factors must be accomplished. As the number of sub-blocks and rotation factors increases, PAR reduction improves, such that complexity increases exponentially and the process delay occurs simultaneously. Therefore a technique that reduces PAR, which is almost close to optimal, and the amount of calculation is desired. In this paper a new method using genetic algorithm(GA), which is widely used to search for a point that is globally optimal in many problems, is proposed to search for a rotation factor that reduces simultaneously both the PAR and the amount of calculation, such that the complexity of calculation and the process time are reduced at the same time, Comparison is performed between the proposed method and the various techniques developed previously. The superiority of proposed method is presented by demonstrating the reduction of complexity while a similar PAR reduction is obtained.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.52 no.7
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• pp.421-428
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• 2003

After the cable is installed, many geometric factors, such as bowing types of the cable and the length difference of the cable between each minor section will cause the impedance unbalance between cables. The impedance unbalance will increase or decrease the sheath circulating currents, which are critical to human safety and sustaining the capabilities of electric power. Accordingly, in this paper, a new method is also proposed to reduce the sheath circulating currents and an reduction equipment according to the theory of the new method is developed. The reduction equipment is tested when the cable is on service. The test results show that it can reduce the sheath circulating currents by up to 97.8［%］. This confirms the validation of the new method and the reduction equipment, and assures the safe operation of the transmission cables. In order to illustrate the safe operation of the cable with new current reduction equipment at transient state due to lightning and single line-to-ground fault, extensive simulations have been made. Then the protection scheme of sheath circulating currents reduction equipment is proposed by adopting the new device of RDP(Reduction Device Protector).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.73-82
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• 2005

Test data volume and power consumption for scan vectors are two major problems in system-on-a-chip testing. Therefore, this paper proposes a new test data compression/decompression method for low power testing. The method is based on analyzing the factors that influence test parameters: compression ratio, power reduction and hardware overhead. To improve the compression ratio and the power reduction ratio, the proposed method is based on Modified Statistical Coding (MSC), Input Reduction (IR) scheme and the algorithms of reordering scan flip-flops and reordering test pattern sequence in a preprocessing step. Unlike previous approaches using the CSR architecture, the proposed method is to compress original test data, not $T_{diff}$, and decompress the compressed test data without the CSR architecture. Therefore, the proposed method leads to better compression ratio with lower hardware overhead and lower power consumption than previous works. An experimental comparison on ISCAS '89 benchmark circuits validates the proposed method.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.168-174
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• 2012

This paper describes a novel global on-chip interconnect scheme, in which a one UI-delayed symbol as well as the current symbol is sent for easing the sensing operation at receiver end. With this approach, the voltage swing on the channel for reliable sensing can be reduced, resulting in performance improvement in terms of power consumption, peak current, and delay spread due to PVT variations, as compared to the conventional repeater insertion schemes. Evaluation for on-chip interconnects having various lengths in a 130 nm CMOS process indicated that the proposed on-chip interconnect scheme achieved a power reduction of up to 71.3%. The peak current during data transmission and the delay spread due to PVT variations were also reduced by as much as 52.1% and 65.3%, respectively.