• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.114-126
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• 2013

In this paper, we present a set of methodologies to model the electromagnetic susceptibility (EMS) testing of I/O buffers for mobile system memory based on the bulk current injection (BCI) method. An efficient equivalent circuit model is developed for the current injection probe, line impedance stabilization network (LISN), printed circuit board (PCB), and package. The simulation results show good correlation with the measurements and thus, the work presented here will enable electromagnetic susceptibility analysis at the integrated circuit (IC) design stage.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.143-146
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• 2011

A 50-MS/s 10-bit pipelined ADC with 1.2Vpp differential input range is proposed in this paper. The designed pipelined ADC consists of eight stage of 1.5bit/stage, one stage of 2bit/stage, digital error correction block, bias & reference driver, and clock generator. 1.5bit/stage is consists of sub-ADC, DAC and gain stage, Specially, a sample-and hold amplifier (SHA) is removed in the designed pipelined ADC to reduce the hardware and power consumption. Also, the proposed bootstrapped switch improves the Linearity of the input analog switch and the dynamic performance of the total ADC. The reference voltage was driven by using the on-chip reference driver without external reference. The proposed pipelined ADC was designed by using a 0.18um 1-poly 5-metal CMOS process with 1.8V supply. The total area including the power decoupling capacitor and power consumption are $0.95mm^2$ and 60mW, respectively. Also, the simulation result shows the ENOB of 9.3-bit at the Nyquist sampling rate.

• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.1399-1401
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• 2000

This paper presents a novel simulation of dynamic voltages in AT-fed railway power supply. Proposed algorithm is efficient and simple by using the circuit decoupling and iteration method. To verify the proposed method, we used real condition operating data and performed a several case studies. Under train is constant power, we separated each AT section to calculate a loop current, train voltage on any position. Finally, this result utilizes a planning and operation of electrical railway systems.

• Journal of Power Electronics
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• v.17 no.2
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• pp.411-421
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• 2017

An approach based on a 2D lumped model is presented to quantify the voltage transfer gain (VTG) in power converter low power planes. The advantage of the modeling approach is the ease with which typical noise reduction devices such as decoupling capacitors or ferrite beads can be integrated into the model. This feature is enforced by a new modular approach based on effective matrix partitioning, which is presented in the paper. This partitioning is used to decouple power plane equations from external device impedance, which avoids the need for rewriting of a whole set of equation at every change. The model is quickly solved in the frequency domain, which is well suited for an automated layout optimization algorithm. Using frequency domain modeling also allows the integration of frequency-dependent devices such inductors and capacitors, which are required for realistic computation results. In order to check the precision of the modeling approach, VTGs for several layout configurations are computed and compared with experimental measurements based on scattering parameters.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.4
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• pp.336-344
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• 2017

This paper presents the three-port DC-DC converter modeling and controller design procedure, which is part of the solid-state transformer (SST) to interface medium voltage AC grid to bipolar DC distribution network. Due to the high primary side DC link voltage, the proposed converter employs the three-level neutral point clamped (NPC) topology at the primary side and 2-two level half bridge circuits for each DC distribution network. For the proposed converter particular structure, this paper conducts modeling the three winding transformer and the power transfer between each port. A decoupling method is adopted to simplify the power transfer model. The voltage controller design procedure is presented. In addition, the output current sharing controller is employed for current balancing between the parallel-connected secondary output ports. The proposed circuit and controller performance are verified by experimental results using a 30 kW prototype SST system.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.48 no.1
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• pp.63-72
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• 2020

As the design complexity and performances are increased in satellite electronic board, noise related problems are also increased. To minimize the noise issues, various design improvements are performed by power integrity and signal integrity analysis in this research. Static power and dynamic power design are reviewed and improved by DC IR drop and power impedance analysis. Signal integrity design is reviewed and improved by time domain signal wave analysis and PCB(Printed Circuit Board) design modifications. And also power planes resonance modes are checked and mitigation measures are verified by simulation. Finally, it is checked that radiated noise is reduced after design improvements by EMC(Electro Magnetic Compatibility) RE(Radiated Emission) measurement results.

• Proceedings of the KIPE Conference
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• 2014.11a
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• pp.107-108
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• 2014

본 논문에서는 디커플링 회로가 포함된 PV-AC 모듈형 플라이백 인버터의 전류 센서리스(Sensorless) MPPT(Maximum power point tracking) 제어기법을 제안한다. 기존의 MPPT제어는 각 모듈의 입력단에 존재하는 전압과 전류 센서를 이용하여 최대 전력점을 추종하였다. 본 논문에서는 전력 변환장치의 저 가격화를 위해 MPPT 제어에 요구되는 전류 센서를 사용하지 않는 센서리스 MPPT 기법을 제안한다. 제안한 기법은 시뮬레이션과 실험을 통해 검증하였다.

• Proceedings of the KIPE Conference
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• 2020.08a
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• pp.34-36
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• 2020

본 논문은 전기자동차용 탑재형 충전기에 사용되는 능동 전력 디커플링 회로의 커패시턴스 저감 기법을 제안한다. 탑재형 충전기의 허용 DC-link 전압 리플과 커패시턴스 사이의 관계를 분석하고, 허용 리플 크기에 따른 최적 커패시턴스의 크기를 도출한다. 제안하는 설계 기법은 시뮬레이션 및 실험 결과를 기반으로 검증한다.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.75-79
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• 2013

A power distribution network (PDN) is a network that provides connection between the voltage source supply and the power/ground terminals of a microprocessor chip. It consists of a voltage regulator module, a printed circuit board, a package substrate, a microprocessor chip as well as decoupling capacitors. For power integrity analysis, the board and package layouts have to be transformed into an electrical network of resistor, inductor and capacitor components which may be expressed using the S-parameters models. This modeling process generally takes from several hours up to a few days for a complete board or package layout. When the board and package layouts change, they need to be re-extracted and the S-parameters models also need to be re-generated for power integrity assessment. This not only consumes a lot of resources such as time and manpower, the task of PDN modeling is also tedious and mundane. In this paper, a block-based PDN modeling is proposed. Here, the board or package layout is partitioned into sub-blocks and each of them is modeled independently. In the event of a change in power rails routing, only the affected sub-blocks will be reextracted and re-modeled. Simulation results show that the proposed block-based PDN modeling not only can save at least 75% of processing time but it can, at the same time, keep the modeling accuracy on par with the traditional PDN modeling methodology.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.4
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• pp.635-641
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• 1998

This paper presents development of a small size LNA operating at 824 ∼ 849 MHz used for a receiver of a CELLULAR CDMA Base station and a transponder. Using resistive decoupling circuits, a signal at low frequency is dissipated by a resistor. This design method increases the stability of the LNA and is suitable for input stage matching. The LNA consists of low noise GaAs FET ATF-10136 and internally matched VNA-25. The LNA is fabricated with both the RF circuit and the self-bias circuits in aluminum housing. As a result, the characteristics of the LNA implemented here shows above 35dB in gain and below 0.9dB in noise figure, 18.6dBm P1dB power, a typical two tone IM3, -31.17dB with single carrier backed off 10dB from P1dB.