• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.3
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• pp.184-196
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for precision measurement of current flowing through a secondary cell battery in a battery management system (BMS). The proposed modulator implements two switched capacitor integrators and a single-bit comparator with peripheral circuits such as a non-overlapping clock generator and a bias circuit. The proposed structure is designed to be applied to low-side current sensing method with low common mode input voltage. Using the low-side current measurement method has the advantage of reducing the burden on the circuit design. In addition, the ±30mV input voltage is resolved by the ADC with 15-bit resolution, eliminating the need for an additional programmable gain amplifier (PGA). The proposed a single-bit 2nd-order delta-sigma modulator has been implemented in a 350-nm CMOS process. It achieves 95.46-dB signal-to-noise-and-distortion ratio (SNDR), 96.01-dB spurious-free dynamic range (SFDR), and 15.56-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 400 for 5-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 670×490 ㎛2 and 414 ㎼, respectively.

• Journal of Ocean Engineering and Technology
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• v.33 no.2
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• pp.168-177
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• 2019

KRISO (Korea Research Institute of Ship & Ocean Engineering) started a project to develop the core algorithms for autonomous intervention using an underwater robot in 2017. This paper introduces the development of the robot platform for the core algorithms, which is an ROV (Remotely Operated Vehicle) type with one 7-function manipulator. Before the detailed design of the robot platform, the 7E-MINI arm of the ECA Group was selected as the manipulator. It is an electrical type, with a weight of 51 kg in air (30 kg in water) and a full reach of 1.4 m. To design a platform with a small size and light weight to fit in a water tank, the medium-size manipulator was placed on the center of platform, and the structural analysis of the body frame was conducted by ABAQUS. The robot had an IMU (Inertial Measurement Unit), a DVL (Doppler Velocity Log), and a depth sensor for measuring the underwater position and attitude. To control the robot motion, eight thrusters were installed, four for vertical and the rest for horizontal motion. The operation system was composed of an on-board control station and operation S/W. The former included devices such as a 300 VDC power supplier, Fiber-Optic (F/O) to Ethernet communication converter, and main control PC. The latter was developed using an ROS (Robot Operation System) based on Linux. The basic performance of the manufactured robot platform was verified through a water tank test, where the robot was manually operated using a joystick, and the robot motion and attitude variation that resulted from the manipulator movement were closely observed.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.22 no.3
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• pp.1-12
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• 2021

Technologies for an MVDC(medium voltage direct current) distribution system are being considered as an effective alternative to overcome the interconnection delay issues of PV systems. However, the implementation of a DC distribution system might lead to economic problems because of the development of DC devices. Therefore, this paper deals with the scale of a PV plant based on its capacity and proposes hosting-capacity models for PV systems to establish a network to evaluate the feasibility of an MVDC distribution system. The proposed models can be classified as AC and DC distribution systems by the power-supply method. PV systems with hundreds of MW, dozens of MW, and a few MW can be categorized as large-scale, medium-scale, and small-scale models, respectively. This paper also performed modeling for an economic evaluation of MVDC distribution system by considering both the cost of AC and DC network construction, converter replacement, operation, etc. The profit was composed of the SMP and REC rate of a PV plant. A simulation for economic evaluation was done for the MVDC distribution system using the present worth and equal-principal costs repayment method. The results confirmed that the proposed model is a useful tool to evaluate economic issues of a DC distribution system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.670-680
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• 2010

A low power single-chip CMOS receiver for 60 GHz mobile application are proposed in this paper. The single-chip receiver consists of a 4-stage current re-use LNA with under 4 dB NF, Cgs compensating resistive mixer with -9.4 dB conversion gain, Ka-band low phase noise VCO with -113 dBc/Hz phase noise at 1 MHz offset from 26.89 GHz, high-suppression frequency doubler with -0.45 dB conversion gain, and 2-stage current re-use drive amplifier. The size of the fabricated receiver using a standard 0.13 ${\mu}m$ CMOS technology is 2.67 mm$\times$0.75 mm including probing pads. An RF bandwidth is 6.2 GHz, from 55 to 61.2 GHz and an LO tuning range is 7.14 GHz, from 48.45 GHz to 55.59 GHz. The If bandwidth is 5.25 GHz(4.75~10 GHz) The conversion gain and input P1 dB are -9.5 dB and -12.5 dBm, respectively, at RF frequency of 59 GHz. The proposed single-chip receiver describes very good noise performances and linearity with very low DC power consumption of only 21.9 mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.58-68
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• 2006

This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2004.04a
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• pp.5-9
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• 2004

In this paper, we studied the OCT(Optical Coherence Tomography) system which it has been extensively studied because of having some advantages such as high resolution cross-sectional images, low cost, and small size configuration. A basic principle of OCT system is Michelson interferometer. The characteristics of light source determine the resolution and the transmission depth. As a results, the light source have a commercial SLD with a central wavelength of 1,285 nm and FWHM(Full Width at Half Maximum) of 35.3 nm. The optical delay line part is necessary to equal of the optical path length with scattered light or reflected light from sample. In order to equal the optical path length, the stage which is attached to reference mirror is moved linearly by step motor And the interferometer is configured with the Michelson interferometer using single mod fiber, the scanner can be focused of the sample by using the reference arm. Also, the 2-dimensional cross-sectional images were measured with scanning the transverse direction of the sample by using step motor. After detecting the internal signal of lateral direction at a paint of sample, scanner is moved to obtain the cross-sectional image of 2-demensional by using step motor. Photodiode has been used which has high detection sensitivity, excellent noise characteristic, and dynamic range from 800 nm to 1,700 nm. It is detected mixed small signal between noise and interference signal with high frequency After filtering and amplifying this signal, only envelope curve of interference signal is detected. And then, cross-sectional image is shown through converting this signal into digitalized signal using A／D converter. The resolution of the OCT system is about 30$\mu\textrm{m}$ which corresponds to the theoretical resolution. Also, the cross-sectional image of ping-pong ball is measured. The OCT system is configured with Michelson interferometer which has a low contrast because of reducing the power of feedback interference light. Such a problem is overcomed by using the improved inteferometer. Also, in order to obtain the cross-sectional image within a short time, it is necessary to reduce the measurement time for improving the optical delay line.