• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.8
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• pp.1464-1474
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• 1994

GPS(Global Positioning System)is a satellite-based navigation system that we can survey where we are, anywhere and anytime. In this paper, delay-lock loop of the receiver which detects the navigation data is theoretically analyzed, and designed using the digital logic circuit. Also logic operations for the synchronization are analyzed. The designed system consists of the correlator which correlates the received C/A code and the generated C/A code in the receiver, the C/A code generator which generates C/A code of selected satellite, and the direct digital clock syntheizer which generates the clock of the C/A code generator to control the C/A code phase and clock rate. From the analyses results of the proposed digital delay-lock loop system, the system has the detection propertied over 90% when its input signal power is above-113.98dB. The influence of input signal variation of digital delay loop, which is the input of A/D converter, is investigated and the performance is analyzed with the variation of threshold level via the computer simulation. The logic simulation results show that the designed system detects precisely the GPS navigation data.

• Proceedings of the KIEE Conference
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• 2002.11d
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• pp.197-199
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• 2002

The invention of VHDL(Very High Speed Integrated Circuit Hardware Description Language), Technical language of Hardware, is a kind of turning point in digital circuit designing, which is being more and more complicated and integrated. Because of its excellency in expression ability of hardware, VHDL is not only used in designing Hardware but also in simulation for verification, and in exchange and conservation, composition of the data of designs, and in many other ways. Especially, It is very important that VHDL is a Technical language of Hardware standardized by IEEE, intenational body with an authority. The biggest problem in modern circuit designing can be pointed out in two way. One is a problem how to process the rapidly being complicated circuit complexity. The other is minimizing the period of designing and manufacturing to survive in a cutthroat competition. To promote the use of VHDL, more than a simple use of simulation by VHDL, it is requested to use VHDL in composing logical circuit with chip manufacturing. And, by developing the quality of designing technique, it can contribute for development in domestic industry related to ASIC designing. In this paper in designing SMPS(Switching mode power supply), programming PWM by VHDL, it can print static voltage by the variable load, connect computer to chip with byteblaster, and download in Max(EPM7064SLCS4 - 5)chip of ALTER. To achieve this, it is supposed to use VHDL in modeling, simulating, compositing logic and product of the FPGA chip. Despite its limit in size and operating speed caused by the specific property of FPGA chip, it can be said that this method should be introduced more aggressively because of its prompt realization after designing.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.35 no.3
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• pp.589-597
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• 2015

Wave energy harvesting system using OWC(Oscillating Water Column) and MB (Movable Body) attached at the caisson breakwater was studied. This system was suggested to maximize wave energy extraction using resonant phenomena of oscillating water column and buoy in wave channel (Park et al., 2014). Not only incident waves but also reflected waves from the breakwater can be used as sources of exciting force for harvesting wave energy efficiently. Using Galerkin finite model based on the linear wave theory (Park, 1991), the performance of the system was evaluated for various damping ratios of power take off system. Numerical results show that the proposed system is excellent in efficiency compared with that of conventional system and the performance of the system is governed by the resonance of oscillating water column in the wave channel. In addition, the additional efforts to minimize viscous damping was found to be necessary because viscous damping occurring in the channel and around the moving buoy is significant in generation efficiency.

• The Journal of the Korea Contents Association
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• v.6 no.1
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• pp.8-13
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• 2006

In this thesis, an automatic door lock system using a dual tone multiple frequency(DTMF) signal generated as pushing the key button of mobile phone is proposed and implemented. This system consists of a transmitter module and a receiver module for processing the DTMF signal of mobile phone. The DTMF signal of mobile phone connected with ear-phone jack enter into the input terminal of DTMF receiver and those are encoded by a code-converter with 4-bits binary format in the DTMF receiver. The encoded output signals are transmitted to the amplitude shift keying(ASK) modulator of transmitter module and the modulated ASK signals which are converted into radio frequency(RF) signals propagate in a free space. The RF signals passed through a free space are demodulated by the ASK demodulator of receiver module and the demodulated ASK signals are sent to a micro-controller unit(MCU). The output signals processed by the MCU are compared with the secreted identification number which is prerecorded in a microprocessor and are transferred to a power relay. If the result is the same, the automatic door lock system opens a door. In the opposite case, it maintains closing the door. The implemented automatic door lock system operates well in mobile environments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1B
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• pp.183-192
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• 2000

In this paper, the dual looped CMOS PLL with 3-250MHz input locking range at a single 13.3V is designed. This paper proposed a new PLL architecture with a current pumping algorithm to improve voltage-to-frequencylinearity of VCO(Voltage Controlled Oscillator). The designed VCO operates at a wide frequency range of75.8MHz-lGHz with a high linearity. Also, PFD(Phase frequency Detector) circuit preventing voltage fluctuation of the charge pump with loop filter circuit under the locked condition is designed. The simulation results of the PLL using 0.6 um N-well single poly triple metal CMOS technology illustrate a locking time of 3.5 us, a power dissipation of 92mW at 1GHz operating frequency with 125MHz of input frequency. Measured results show that the phase noise of VCO with V-I converter is -100.3dBc/Hz at a 100kHz offset frequency.

• The Journal of Korea Robotics Society
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• v.8 no.1
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• pp.29-36
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• 2013

This paper presents a sensitivity optimization of a MEMS (microelectromechanical systems) gyroscope for a magnet-gyro system. The magnet-gyro system, which is a guidance system for a AGV (automatic or automated guided vehicle), uses a magnet positioning system and a yaw gyroscope. The magnet positioning system measures magnetism of a cylindrical magnet embedded on the floor, and AGV is guided by the motion direction angle calculated with the measured magnetism. If the magnet positioning system does not measure the magnetism, the AGV is guided by using angular velocity measured with the gyroscope. The gyroscope used for the magnet-gyro system is usually MEMS type. Because the MEMS gyroscope is made from the process technology in semiconductor device fabrication, it has small size, low-power and low price. However, the MEMS gyroscope has drift phenomenon caused by noise and calculation error. Precision ADC (analog to digital converter) and accurate sensitivity are needed to minimize the drift phenomenon. Therefore, this paper proposes the method of the sensitivity optimization of the MEMS gyroscope using DEAS (dynamic encoding algorithm for searches). For experiment, we used the AGV mounted with a laser navigation system which is able to measure accurate position of the AGV and compared result by the sensitivity value calculated by the proposed method with result by the sensitivity in specification of the MEMS gyroscope. In experimental results, we verified that the sensitivity value through the proposed method can calculate more accurate motion direction angle of the AGV.

• Journal of Sensor Science and Technology
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• v.15 no.1
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• pp.34-39
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• 2006

This study provides the electrical model of combustible catalytic gas sensor. Physical characteristics such as thermal behavior, resistance change were included in this model. The finite element method analysis for sensor device structure showed that the thermal behavior of sensor is expressed in a simple electrical equivalent circuit that consists of a resistor, a capacitor and a current source. This thermal equivalent circuit interfaces with real electrical circuit using two parts. One is 'power to heat' converter. The other is temperature dependent variable resistor. These parts realized with the analog behavior devices of the SPICE library. The gas response tendency was represented from the mass transferring limitation theory and the combustion theory. In this model, Gas concentration that is expressed in voltage at the model, is converted to heat and is flowed to the thermal equivalent circuit. This model is tested in several circuit simulations. The resistance change of device, the delay time due to thermal capacity, the gas responses output voltage that are calculated from SPICE simulations correspond well to real results from measuring in electrical circuits. Also good simulation result can be produced in the more complicated circuit that includes amplifier, bios circiut, buffer part.

• Journal of the Institute of Convergence Signal Processing
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• v.14 no.4
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• pp.249-254
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• 2013

A fast multiplier and ADC are essential to process the analog signals in real time. The double-base number system(DBNS) is known as an efficient method for this purpose. The DBNS uses the numbers 2 and 3 as the base numbers simultaneously. The system has an advantage of fast multiplication, less chip area, and low power consumption compared to the binary multiplier. However, the inherent errors of the log number's intrinsic tolerance in DBNS are accumulated in a FIR digital filter, so the signal-to-noise ratio(SNR) has a tendency to be degraded. In this paper, the nonlinear encoder of ADC is designed to compensate the accumulated errors of DBNS by analysing the error distributions of various filter coefficients. The new ADC does not sacrifice its own advantages because the encoder circuits are modified only. The experiments were done with an FIR filters those were designed to have -70dB of SNR in stop band. The proposed nonlinear ADC encoder could drop the SNR to -45dB in stop band, in contrast to -35dB with the linear encoder.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2014.10a
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• pp.17-18
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• 2014

Wave energy generation system is sorted as oscillating water chamber type, over topping device type and wave activating body type. The wave activating body type converts from wave energy to kinetic of the machine one and the power generation amount increases while the motion of a activating body increases. In this paper the wave energy convertor consists of a main body which has a generation system and the activating body. They are connected by a bar type bridge. The twisting moment and angular velocity at a shaft of convertor are calculated when various condition of the incident wave, a diversity of connection methods between the main body and the activating body. It can be used as basic idea for determining the design of wave activating body type convertor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.10
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• pp.1-6
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• 2007

Wireless Self-Powered Temperature Sensor for UHF Sensor Tags which are basic device for construction of ubiquitous sensor network is proposed. The key parameters of the target specification are resolution of $0.1\;^{\circ}C$ per output bit, below 1.5 V of operating voltage and below 5 uW of power consumption during sensing operation. Temperature sensor circuit consists of PTAT current generator, band gap reference circuit generating both reference voltage and current, Sigma-Delta Converter, and Digital Counter. Simulated maximum resolution was $0.23\;^{\circ}C/bit$ in 11-bit output. The proposed temperature sensor was fabricated by using a 0.25 m CMOS process. The chip area is $0.32\;{\times}\;0.22\;mm$ and the operating frequency is 2 MHz. Measured resolution from fabricated temperature sensor was $4\;^{\circ}C/bit$ in 8-bit output for the temperature range from $10^{\circ}C$ to $80^{\circ}C$.