• Title/Summary/Keyword: Power converter

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High-Speed CMOS Binary Image Sensor with Gate/Body-Tied PMOSFET-Type Photodetector

  • Choi, Byoung-Soo;Jo, Sung-Hyun;Bae, Myunghan;Kim, Jeongyeob;Choi, Pyung;Shin, Jang-Kyoo
    • Journal of Sensor Science and Technology
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    • v.23 no.5
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    • pp.332-336
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    • 2014
  • In this paper, we propose a complementary metal oxide semiconductor (CMOS) binary image sensor with a gate/body-tied (GBT) PMOSFET-type photodetector for high-speed operation. The GBT photodetector of an active pixel sensor (APS) consists of a floating gate ($n^+$-polysilicon) tied to the body (n-well) of the PMOSFET. The p-n junction photodiode that is used in a conventional APS has a good dynamic range but low photosensitivity. On the other hand, a high-gain GBT photodetector has a high level of photosensitivity but a narrow dynamic range. In addition, the pixel size of the GBT photodetector APS is less than that of the conventional photodiode APS because of its use of a PMOSFET-type photodetector, enabling increased image resolution. A CMOS binary image sensor can be designed with simple circuits, as a complex analog to digital converter (ADC) is not required for binary processing. Because of this feature, the binary image sensor has low power consumption and high speed, with the ability to switch back and forth between a binary mode and an analog mode. The proposed CMOS binary image sensor was simulated and designed using a standard CMOS $0.18{\mu}m$ process.

RESEARCH ON MODULARIZED DESIGN AND PERFORMANCE ASSESSMENT BASED ON MULTI-DRIVER OFF-ROAD VEHICLE DRIVING-LINE

  • Yi, J.J.;Yu, B.;Hu, D.Q.;Li, C.G.
    • International Journal of Automotive Technology
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    • v.8 no.3
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    • pp.375-382
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    • 2007
  • The multi-driver off-road vehicle drive-line consists of many components, with close connections among them. In order to design and analyze the drive-line efficiently, a modular methodology should be taken. The aim of a modular approach to the modeling of complex systems is to support behavior analysis and simulation in an iterative and thus complex engineering process, by using encapsulated submodels of components and of their interfaces. Multi-driver off-road vehicles are comparatively complicated. The driving-line is an important core part to the vehicle, it has a significant contribution to the performance. Multi-driver off-road vehicles have complex driving-lines, so performance is heavily dependent on the driving-line. A typical off-road vehicle's driving-line system consists of a torque converter, transmission, transfer case and driving-axles, which transfers the power generated by the engine and distributes it effectively to the driving wheels according to the road condition. According to its main function, this paper proposes a modularized approach for design and evaluation of the vehicle's driving-line. It can be used to effectively estimate the performance of the driving-line during the concept design stage. Through an appropriate analysis and assessment method, an optimal design can be reached. This method has been applied to practical vehicle design, it can improve the design efficiency and is convenient to assess and validate the performance of a vehicle, especially of multi-driver off-road vehicles.

Development of Super-capacitor Battery Charger System based on Photovoltaic Module for Agricultural Electric Carriers

  • Kang, Eonuck;Pratama, Pandu Sandi;Byun, Jaeyoung;Supeno, Destiani;Chung, Sungwon;Choi, Wonsik
    • Journal of Biosystems Engineering
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    • v.43 no.2
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    • pp.94-102
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    • 2018
  • Purpose: In this study, a maintenance free super-capacitor battery charging system based on the photovoltaic module, to be used in agricultural electric carriers, was developed and its charging characteristics were studied in detail. Methods: At first, the electric carrier system configuration is introduced and the electric control components are presented. The super-capacitor batteries and photovoltaic module used in the experiment are specified. Next, the developed charging system consisting of a constant current / constant voltage Buck converter as the charging device and a super-capacitor cell as a balancing device are initiated. The proposed circuit design, a developed PCB layout of each device and a proportional control to check the current and voltage during the charging process are outlined. An experiment was carried out using a developed prototype to clarify the effectiveness of the proposed system. A power analyzer was used to measure the current and voltage during charging to evaluate the efficiency of the energy storage device. Finally, the conclusions of this research are presented. Results: The experimental results show that the proposed system successfully controls the charging current and balances the battery voltage. The maximum voltage of the super-capacitor battery obtained by using the proposed battery charger is 16.2 V, and the maximum charging current is 20 A. It was found that the charging time was less than an hour through the duty ratio of 95% or more. Conclusions: The developed battery charging system was successfully implemented on the agricultural electric carriers.

Harmonic Reduction of Electric Propulsion System by Current Injection (전류주입에 의한 전기추진시스템의 고조파 저감)

  • Kim, Jong-Su;Han, Won-Hui;Seo, Dong-Hoan
    • Journal of the Korean Society of Marine Environment & Safety
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    • v.18 no.4
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    • pp.360-364
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    • 2012
  • AC to DC converter that consists of relatively simple diode rectifier devices has been widely used in the field of the electric propulsion system. Also, since this rectifier includes large harmonics in the input current, a variety of researches have been developed to reduce the harmonics. The proposed method of this paper is to reduce the harmonics included in the input current of rectifiers and propulsion motor by injecting the output current of diode rectifier into the input of them. In addition, the proposed method ensures electrical safety through the respective isolation of the injection current, the source, and the loads using the Wye-Delta insulating transformer applied in current injection device that is installed in the input circuit of rectifiers and propulsion motor. The proposed method is simulated by applying to the electric propulsion ship that is currently operating. We confirm the validity of the proposed method compared with conventional power conversion system.

Design and Implementation of the RF Systems for Bi-directional Wireless Capsule Endoscopes

  • Moon, Yeon-Kwan;Lee, Jyung-Hyun;Park, Hee-Joon;Lee, Ju-Gab;Ryu, Jae-Jong;Lee, Wu-Seong;Woo, Sang-Hyo;Won, Chul-Ho;Cho, Jin-Ho;Choi, Hyun-Chul
    • Journal of Korea Multimedia Society
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    • v.9 no.12
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    • pp.1669-1680
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    • 2006
  • This paper explains that the RF systems for hi-directional wireless capsule endoscopes were designed and implemented. The designed RF systems for a capsule endoscope can transmit the images of intestines from the inside to the outside of a body and the behavior of the capsules can be controlled by an external controller simultaneously. The hi-directional wireless capsule endoscope consists of a CMOS image sensor, FPGA, LED, battery, DC to DC Converter, transmitter, receiver, and antennas. The transmitter and receiver which were used in the hi-directional capsule endoscope, were designed and fabricated with $10mm(diameter){\times}3.2mm(thickness)$ dimensions taking into the MPE, power consumption, system size, signal to noise ratio and modulation method. The RF systems designed and implemented for the hi-directional wireless capsule endoscopes system were verified by in-vivo experiments. As a result, the RF systems for the hi-directional wireless capsule endoscopes satisfied the design specifications.

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Implementation of Data Protocol Conversion System for High-end CMOS Image Sensors Equipped with SMIA CCP2 Serial Interface (SMIA CCP2 직렬 인터페이스를 가지는 고기능 이미지 센서를 위한 데이터 프로토콜 변환 시스템의 구현)

  • Kim, Nam-Ho;Park, Hyun-Sang
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.10 no.4
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    • pp.753-758
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    • 2009
  • Recently the high-end CMOS image sensors are developed, conforming to the SMIA CCP2 specification, which is a high-speed low-power serial interface based on LVDS technology. But this kind of technology trend makes the existing equipments are no longer useful, although their capability is still good enough to handle the recent image sensors if there was no interfacing problem. In this paper, we propose and realize a data protocol conversion system that translates the SMIA CCP2 serial signals into the existing 10-bit parallel signals. The proposed system is composed of a de-serializer and a FPCA chip, and thus can be constructed on a small PCB which enables easy integration between the existing equipments and the new high-end image sensors. Besides, the maximum transfer rate by the SMIA specification is also achieved on the implemented system. So it is expected that the implemented system can be used as a general-purpose protocol converter in a variety of sensor-related application fields.

An Enhancement of Speaker Location System Using the Low-frequency Phase Restoration Algorithm and Its Implementation (저주파 위상 복원 알고리듬을 이용한 화자 위치 추적 시스템의 성능 개선과 구현)

  • 이학주;차일환;윤대희;이충용
    • The Journal of the Acoustical Society of Korea
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    • v.20 no.4
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    • pp.22-28
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    • 2001
  • This paper describes the implementation of a robust speaker position location system using the voice signal received by microphone array. To be robust to the reverberation which is the major factor of the performance degradation, low-frequency phase restoration algorithm which eliminates the influence of reverberations using the low-frequency information of the CPSP function is proposed. The implemented real-time system consists of a general purpose DSP (TMS320C31 of Texas instruments), analog part which contains amplifiers and filters, and digital part which is composed of the external memory and 12-bit A/D converter. In the real conference room environment, the implemented system that was constructed by the proposed algorithms showed better performance than the conventional system. The error of the TDOA estimation reduced more than 15 samples.

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A study on development of 1kW SOFC test system (1kW급 연료전지 평가시스템 개발에 관한 연구)

  • Hwang, Hyun Suk;Lee, Sanghoon;Lee, Juyoung
    • Journal of Satellite, Information and Communications
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    • v.11 no.3
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    • pp.24-27
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    • 2016
  • In this study, a 1kW Solid Oxide Fuel Cell(SOFC) test system was developed. A SOFC is the most promising power system to provide the higher efficient(over 50%) for house application area(1~10kW). To develop the optimized test system, the temperature control module that controls the preprocess and reaction condition, the flow control module that controls of the mass of reactants, and the electric loader that tests the discharge performance condition, etc. The temperature control module was designed to provide the high control resolution(under $1^{\circ}C$ at $750^{\circ}C$ of operating temperature) using K-type thermal couple. The flow control module was designed control blower and heater precisely using the phase control method. And the electric loader is designed that provide CV, CC, CR discharge mode and minimized the operating error adopting the independent DC-DC converter on analog input and output module. The performance of the developed SOFC test system showed that the accuracy of stack voltage was 0.15% at 80V and stack current was 0.1% at 100A.

A 12b 100 MS/s Three-Step Hybrid Pipeline ADC Based on Time-Interleaved SAR ADCs

  • Park, Jun-Sang;An, Tai-Ji;Cho, Suk-Hee;Kim, Yong-Min;Ahn, Gil-Cho;Roh, Ji-Hyun;Lee, Mun-Kyo;Nah, Sun-Phil;Lee, Seung-Hoon
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.2
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    • pp.189-197
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    • 2014
  • This work proposes a 12b 100 MS/s $0.11{\mu}m$ CMOS three-step hybrid pipeline ADC for high-speed communication and mobile display systems requiring high resolution, low power, and small size. The first stage based on time-interleaved dual-channel SAR ADCs properly handles the Nyquist-rate input without a dedicated SHA. An input sampling clock for each SAR ADC is synchronized to a reference clock to minimize a sampling-time mismatch between the channels. Only one residue amplifier is employed and shared in the proposed ADC for the first-stage SAR ADCs as well as the MDAC of back-end pipeline stages. The shared amplifier, in particular, reduces performance degradation caused by offset and gain mismatches between two channels of the SAR ADCs. Two separate reference voltages relieve a reference disturbance due to the different operating frequencies of the front-end SAR ADCs and the back-end pipeline stages. The prototype ADC in a $0.11{\mu}m$ CMOS shows the measured DNL and INL within 0.38 LSB and 1.21 LSB, respectively. The ADC occupies an active die area of $1.34mm^2$ and consumes 25.3 mW with a maximum SNDR and SFDR of 60.2 dB and 69.5 dB, respectively, at 1.1 V and 100 MS/s.

Preliminary Research of CZT Based PET System Development in KAERI

  • Jo, Woo Jin;Jeong, Manhee;Kim, Han Soo;Kim, Sang Yeol;Ha, Jang Ho
    • Journal of Radiation Protection and Research
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    • v.41 no.2
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    • pp.81-86
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    • 2016
  • Background: For positron emission tomography (PET) application, cadmium zinc telluride (CZT) has been investigated by several institutes to replace detectors from a conventional system using photomultipliers or Silicon-photomultipliers (SiPMs). The spatial and energy resolution in using CZT can be superior to current scintillator-based state-of-the-art PET detectors. CZT has been under development for several years at the Korea Atomic Energy Research Institute (KAERI) to provide a high performance gamma ray detection, which needs a single crystallinity, a good uniformity, a high stopping power, and a wide band gap. Materials and Methods: Before applying our own grown CZT detectors in the prototype PET system, we investigated preliminary research with a developed discrete type data acquisition (DAQ) system for coincident events at 128 anode pixels and two common cathodes of two CZT detectors from Redlen. Each detector has a $19.4{\times}19.4{\times}6mm^3$ volume size with a 2.2 mm anode pixel pitch. Discrete amplifiers consist of a preamplifier with a gain of $8mV{\cdot}fC^{-1}$ and noise of 55 equivalent noise charge (ENC), a $CR-RC^4$ shaping amplifier with a $5{\mu}s$ peak time, and an analog-to-digital converter (ADC) driver. The DAQ system has 65 mega-sample per second flash ADC, a self and external trigger, and a USB 3.0 interface. Results and Discussion: Characteristics such as the current-to-voltage curve, energy resolution, and electron mobility life-time products for CZT detectors are investigated. In addition, preliminary results of gamma ray imaging using 511 keV of a $^{22}Na$ gamma ray source were obtained. Conclusion: In this study, the DAQ system with a CZT radiation sensor was successfully developed and a PET image was acquired by two sets of the developed DAQ system.