• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.188-191
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• 2000

This paper presents a register scheduling and allocation algorithm for high level synthesis. The proposed algorithm executes the low power scheduling to reduce the switching activity using shut down technique which was not unnecessary the calculation through the extraction DFG from VHDL description. Also, the register allocation algorithm determines the minimum register after the life time analysis of all variable. It is minimum the switching activity using graph coloring technique for low power consumption. The proposed algorithm proves the effect through various filter benchmark to adopt a new scheduling and allocation algorithm considering the low power.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.16 no.6
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• pp.1892-1912
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• 2022

With the massive demand and growth of cloud computing, virtualization plays an important role in providing services to end-users efficiently. However, with the increase in services over Cloud Computing, it is becoming more challenging to manage and run multiple Virtual Machines (VMs) in Cloud Computing because of excessive power consumption. It is thus important to overcome these challenges by adopting an efficient technique to manage and monitor the status of VMs in a cloud environment. Reduction of power/energy consumption can be done by managing VMs more effectively in the datacenters of the cloud environment by switching between the active and inactive states of a VM. As a result, energy consumption reduces carbon emissions, leading to green cloud computing. The proposed Efficient Dynamic VM Scheduling approach minimizes Service Level Agreement (SLA) violations and manages VM migration by lowering the energy consumption effectively along with the balanced load. In the proposed work, VM Scheduling for Efficient Dynamically Migrated VM (VMS-EDMVM) approach first detects the over-utilized host using the Modified Weighted Linear Regression (MWLR) algorithm and along with the dynamic utilization model for an underutilized host. Maximum Power Reduction and Reduced Time (MPRRT) approach has been developed for the VM selection followed by a two-phase Best-Fit CPU, BW (BFCB) VM Scheduling mechanism which is simulated in CloudSim based on the adaptive utilization threshold base. The proposed work achieved a Power consumption of 108.45 kWh, and the total SLA violation was 0.1%. The VM migration count was reduced to 2,202 times, revealing better performance as compared to other methods mentioned in this paper.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.93-100
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• 2004

Test scheduling of SoC (System-on-a-chip) is very important because it is one of the prime methods to minimize the testing time under limited power consumption of SoC. In this paper, a heuristic algorithm, in which test resources are selected for groups and arranged based on the size of product of power dissipation and test time together with total power consumption in core-based SoC is proposed. We select test resource groups which has maximum power consumption but does not exceed the constrained power consumption and make the testing time slot of resources in the test resource group to be aligned at the initial position in test space to minimize the idling test time of test resources. The efficiency of proposed algorithm is confirmed by experiment using ITC02 benchmarks.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.257-263
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• 2002

Test scheduling of SoC becomes more important because it is one of the prime methods to minimize the testing time under limited power consumption of SoCs. In this paper, a heuristic algorithm, in which test resources are selected for groups and arranged based on the size of product of power dissipation and test time together with total power consumption in core-based SoCs is proposed. We select test resource groups which has maximum power consumption but does not exceed the constrained power consumption and make the testing time slot of resources in the test resource group to be aligned at the initial position to minimize the idle test time of test resources.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.22-28
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• 2009

As multiprocessors have been widely adopted in embedded systems, task computation energy consumption should be minimized with several low power techniques supported by the multiprocessors. This paper proposes an energy-aware task scheduling algorithm that adopts both dynamic voltage scaling and power shutdown in multiprocessor environments. Considering the timing and energy overhead of power shutdown, the proposed algorithm performs an iterative task assignment and task ordering for multiprocessor systems. In this case, the iterative priority-based task scheduling is adopted to obtain the best solution with the minimized total energy consumption. Total energy consumption is calculated by considering a linear programming model and threshold time of power shutdown. By analyzing experimental results for standard task graphs based on real applications, the resource and timing limitations were analyzed to maximize energy savings. Considering the experimental results, the proposed energy-aware task scheduling provided meaningful performance enhancements over the existing priority-based task scheduling approaches.

• Journal of Communications and Networks
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• v.18 no.3
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• pp.484-492
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• 2016

Smart grid (SG) technology is now elevating the conventional power grid system to one that functions more cooperatively, responsively, and economically. When applied in an SG the demand side management (DSM) technique can improve its reliability by dynamically changing electricity consumption or rescheduling it. In this paper, we propose a new SG scheduling scheme that uses the DSM technique. To achieve effective SG management, we adopt a mixed pricing strategy based on the Rubinstein-Stahl bargaining game and a repeated game model. The proposed game-based pricing strategy provides energy routing for effective energy sharing and allows consumers to make informed decisions regarding their power consumption. Our approach can encourage consumers to schedule their power consumption profiles independently while minimizing their payment and the peak-to-average ratio (PAR). Through a simulation study, it is demonstrated that the proposed scheme can obtain a better performance than other existing schemes in terms of power consumption, price, average payment, etc.

• Journal of information and communication convergence engineering
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• v.16 no.2
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• pp.84-92
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• 2018

For large wireless sensor networks running on battery power, the time synchronization of all sensor nodes is becoming a crucial task for waking up sensor nodes with exact timing and controlling transmission and reception timing. However, as network size increases, this synchronization process tends to require long processing time consume significant power. Furthermore, a naïve synchronization scheduler may leave some nodes unsynchronized. This paper proposes a power-efficient scheduling algorithm for time synchronization utilizing the notion of density, which is defined by the number of neighboring nodes within wireless range. The proposed scheduling algorithm elects a sequence of minimal reference nodes that can complete the synchronization with the smallest possible number of hops and lowest possible power consumption. Additionally, it ensures coverage of all sensor nodes utilizing a two-pass synchronization scheduling process. We implemented the proposed synchronization algorithm in a network simulator. Extensive simulation results demonstrate that the proposed algorithm can reduce the power consumption required for the periodic synchronization process by up to 40% for large sensor networks compared to a simplistic multi-hop synchronization method.

• Journal of Communications and Networks
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• v.16 no.1
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• pp.36-44
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• 2014

Exploiting the energy-delay tradeoff for energy saving is critical for developing green wireless communication systems. In this paper, we investigate the delay-constrained energy-efficient packet transmission. We aim to minimize the energy consumption of multiple randomly arrived packets in an additive white Gaussian noise channel subject to individual packet delay constraints, by taking into account the practical on-off circuit power consumption at the transmitter. First, we consider the offline case, by assuming that the full packet arrival information is known a priori at the transmitter, and formulate the energy minimization problem as a non-convex optimization problem. By exploiting the specific problem structure, we propose an efficient scheduling algorithm to obtain the globally optimal solution. It is shown that the optimal solution consists of two types of scheduling intervals, namely "selected-off" and "always-on" intervals, which correspond to bits-per-joule energy efficiency maximization and "lazy scheduling" rate allocation, respectively. Next, we consider the practical online case where only causal packet arrival information is available. Inspired by the optimal offline solution, we propose a new online scheme. It is shown by simulations that the proposed online scheme has a comparable performance with the optimal offline one and outperforms the design without considering on-off circuit power as well as the other heuristically designed online schemes.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.1
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• pp.37-41
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• 2018

In this paper, we evaluate the power consumption of IEEE802.15.4e TSCH which uses the specific link scheduling scheme proposed in reference[1]. And we also compares it with the power consumption of conventional single channel IEEE802.15.4. The power consumption of IEEE802.15.4e TSCH is smaller than the conventional one under the any conditions of traffic. The reasons can be explained as the followings. Firstly, TSCH does not have backoff time because of using the collision free link scheduling. Secondly, there is the timing difference of MAC offset parameter between TSCH and conventional IEEE802.15.4 Lastly, the devices in TSCH mode sleep during the time slots which are not assigned to itself.

• Journal of Korea Society of Digital Industry and Information Management
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• v.8 no.1
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• pp.41-46
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• 2012

In this paper, An efficient circuit design algorithm considering constraint is proposed. The proposed algorithm sets up in time constraint and area constraint, power consumption constraint for a circuit implementation. First, scheduling process for time constraint. Select the FU(Function Unit) which is satisfied with time constraint among the high level synthesis results. Analyze area and power consumption of selected FUs. Constraint set for area and power constraint. Device selection to see to setting condition. Optimization circuit implementation in selected device. The proposed algorithm compared with [7] and [8] algorithm. Therefore the proposed algorithm is proved an efficient algorithm for optimization circuit implementation.