• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.56-63
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• 2016

This paper presents a novel method for detecting a ghost key at the membrane type keyboard, which has additional resistive coating to the membrane film. Also, the optimal ratio of resistances for detecting a ghost key was designed based on the characteristics of the membrane film. The optimal ratio of resistances was considered to be able to detect the worst case (i.e., difference voltage between normal key and ghost key is minimum). The ability of the proposed methods are evaluated by simulation studies in this paper. In order to verify the proposed method, the experiment was carried out with a designed circuit and A/D (analog to digital) in MCU (micro controller unit). The proposed method is implemented into the membrane type keyboard and is verified by experimental results.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.8
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• pp.770-776
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• 2009

We propose and demonstrate an I/Q demodulator using four-port BPSK demodulator base on additive mixing and reflection-type phase shifter using hybrid technique. Previously, the conventional I/Q demodulator base on multiplicative or additive mixing method divides I/Q signal path from mixer to parallel-to-serial converter. In this paper, we propose new I/Q demodulator without dividing I/Q baseband signal path. The proposed schematic requires half size in implementation and half power consumption in baseband path compared with the conventional receiver. Also, the proposed receiver eliminates parallel-to-serial converter after data decoding. The proposed circuit has been successfully demodulated a QPSK signal with the L-band carrier frequency and 20 Mbps data rate.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.10
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• pp.1123-1130
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• 2015

Network on a chip(NoC) is a communication subsystem between intellectual property(IP) cores in a SoC and improves high performance in the scalability and the power efficiency compared with conventional buses and crossbar switches. NoC needs a synchronizer to overcome the metastability problem between data links. This paper presents a new mesochronous synchronizer(MS) which is composed of selection window generator, selection signal generator, and data buffer. A delay line circuit is used to build selection window in selection window generator based on the delayed clock cycle of transmitted clock and the transmitted clock is compared with local clock to generate a selection signal in the SW(selection window). This MS gets rid of the restriction of metastability by choosing a rising edge or a falling edge of local clock according to the value of selection signal. The simulation results show that the proposed MS operates correctly for all phase differences between a transmitted clock and a local clock.

• Journal of Biosystems Engineering
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• v.43 no.2
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• pp.94-102
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• 2018

Purpose: In this study, a maintenance free super-capacitor battery charging system based on the photovoltaic module, to be used in agricultural electric carriers, was developed and its charging characteristics were studied in detail. Methods: At first, the electric carrier system configuration is introduced and the electric control components are presented. The super-capacitor batteries and photovoltaic module used in the experiment are specified. Next, the developed charging system consisting of a constant current / constant voltage Buck converter as the charging device and a super-capacitor cell as a balancing device are initiated. The proposed circuit design, a developed PCB layout of each device and a proportional control to check the current and voltage during the charging process are outlined. An experiment was carried out using a developed prototype to clarify the effectiveness of the proposed system. A power analyzer was used to measure the current and voltage during charging to evaluate the efficiency of the energy storage device. Finally, the conclusions of this research are presented. Results: The experimental results show that the proposed system successfully controls the charging current and balances the battery voltage. The maximum voltage of the super-capacitor battery obtained by using the proposed battery charger is 16.2 V, and the maximum charging current is 20 A. It was found that the charging time was less than an hour through the duty ratio of 95% or more. Conclusions: The developed battery charging system was successfully implemented on the agricultural electric carriers.

• The Journal of the Korea Contents Association
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• v.6 no.4
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• pp.1-10
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• 2006

In this paper, a broadband RF module is designed and tested for 2.4GHz band applications. The RF module is composed of a low noise amplifier (LNA) with a three stage amplifier, a single ended gate mixer, matching circuits, a hairpin line band pass filter and a Chebyshev low pass filter to convert the radio frequency (RF) into the intermediate frequency (IF). The LNA has a high gain and stability, and the single ended gate mixer has a high conversion gain and wide dynamic range. In the analysis of the broadband RF module, the composite harmonic balance technique is used to analyze the operating characteristics of an RF module circuit. The RF module has a 55.2dB conversion gain with a 1.54dB low noise figure, $-120{\sim}-60dBm$ wide RF power dynamic range, -60dBm low harmonic spectrum and a good isolation factor among the RF, IF, and local oscillator (LO) ports.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.2
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• pp.461-468
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• 2010

This paper presents a simple digital LCD backlight inverter using a single-chip microcontroller. The proposed inverter reduces the ignition voltage and eliminates the current spikes and hence improves the ignition behavior of the cold cathode fluorescent lamp(CCFL). Thus it increases the CCFL's life span. This is achieved by implementing a digital dimming control algorithm, that contains the soft-starting algorithm, all on a single-chip microcontroller. The inverter utilizes the full-bridge resonant circuit topology. The design example along with a simple analysis for the inverter is shown, and the experimental results of the designed prototype results in close agreement with the theoretical analysis and explanation. The overall system's power efficiency is approximately 85%. Compared with conventional inverters, the ignition voltage is reduced by around 30% without any lamp current spike occurring during the dimming control operation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.2
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• pp.397-401
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• 2005

In this paper, we have developed a frequency mixer which can be used as a microwave phase conjugator in the retrodirective array antenna. The retrodirective array, which can reflect the incident wave retrodirertively back to the source direction without any priori information, requires phase conjugators to achieve the phase change of 180 degrees for the incoming signal. frequency mixers can efficiently serve as phase conjugators. The circuit topology is of the 2-port structure to avoid the complexity of LO and Rf signal combination and matching circuits, using a pseudomorphic HEU device. The operating frequencies are 4.0 CHz, 2.01 CHz, and 1.99 CHz for LO, RF, and If signals, respectively. Conversion loss is measured to be -ldB and 1-dB compression point -l5 dBm at the LO power of -10 dBm.

• Journal of Advanced Navigation Technology
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• v.12 no.2
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• pp.122-131
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• 2008

In this paper, an S-band oscillator of the low phase noise property using miniaturized microstrip hairpin shaped ring resonator has been designed and implemented. The TACONIC's RF-35 substrate has a dielectric constant ${\varepsilon}_r$=3.5 a thickness h=20mil a copper thickness t=17 um and loss tangent $tan{\delta}$=0.0025. The designed and implemented 2.45 GHz oscillator shows low phase performance of -100.5 dBc/Hz a 100kHz offset. Output power 20.9 dBm at center frequency 2.45 GHz and harmonic suppression -32 dBc. The circuit was implemented with hybrid technique. But can be fully compatible with the RFIC's, MIC and MMIC due to its entirely planar structure.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.1
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• pp.76-81
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• 2009

A novel design method of time-interleaved subranging ADC is presented. We use the bisection method to let only half of comparators in typical subranging ADC working in every clock cycle. Thus, we are able to reduce the number of comparators by half. It is possible to reduce the die size. An example of 8-bit time-interleaved subranging ADC operates at 40MHz sampling rate and 1.8V supply voltage is demonstrated. The power consumption of the proposed circuit is only 10mV with SPECTRE simulation. Compared with the typical subranging ADC, our bisection method is able to reduce up to 40% in die size.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.33-38
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• 2004

A multi-valued logic(MVL) pass gate is an important element to configure multi-valued logic. In this paper, we designed the Quaternary MIN(QMIN)/negated MIN(QNMIN) gate, the Quaternary MAX(QMAX)/negated MAX(QNMAX) gate using double pass-transistor logic(DPL) with neuron $MOS({\nu}MOS)$ threshold gate. DPL is improved the gate speed without increasing the input capacitance. It has a symmetrical arrangement and double-transmission characteristics. The threshold gates composed by ${\nu}MOS$ down literal circuit(DLC). The proposed gates get the valued to realize various multi threshold voltages. In this paper, these circuits are used 3V power supply voltage and parameter of 0.35um N-Well 2-poly 4-metal CMOS technology, and also represented HSPICE simulation results.