• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 심포지엄 논문집 정보 및 제어부문
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• pp.148-151
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• 2005

This paper proposes a high speed interface using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that convert redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was designed using a 0.35${\mu}m$ standard CMOS Process. Proposed demultiplexer is achieved an operating speed of 3Gb/s with a supply voltage of 3.3V and with power consumption of 48mW. Designed circuit is limited by maximum operating frequency of process. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 3Gb/s in submicron process of high of operating frequency.

• ETRI Journal
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• 제36권4호
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• pp.643-653
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• 2014

To reduce interconnect delay and power consumption while improving chip performance, a three-dimensional integrated circuit (3D IC) has been developed with die-stacking and through-silicon via (TSV) techniques. The power supply problem is one of the essential challenges in 3D IC design because IR-drop caused by insufficient supply voltage in a 3D chip reduces the chip performance. In particular, power bumps and TSVs are placed to minimize IR-drop in a 3D power delivery network. In this paper, we propose a design methodology for 3D power delivery networks to minimize the number of power bumps and TSVs with optimum mesh structure and distribute voltage variation more uniformly by shifting the locations of power bumps and TSVs while satisfying IR-drop constraint. Simulation results show that our method can reduce the voltage variation by 29.7% on average while reducing the number of power bumps and TSVs by 76.2% and 15.4%, respectively.

• Journal of Power Electronics
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• 제9권2호
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• pp.180-187
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• 2009

When converters operate in megahertz range, the passive components and magnetic devices generate high losses. However, the eddy current issues and choices of magnetic cores significantly affect on the design stage. Apart from that, the components' reduction, miniaturization technique and frequency scaling are required as well as improvement in thermal capability, integration technique, circuit topologies and PCB layout optimization. In transformer design, the winding and core losses give great attention to the design stage. From simulation work, it is found that E-25066 material manufactured by AVX could be the most suitable core for high frequency transformer design. By employing planar geometry topology, the material can generate significant power loss savings of more than 67% compared to other materials studied in this work. Furthermore, young researchers can use this information to develop new approaches based on concepts, issues and methodology in the design of magnetic components for high frequency applications.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2006년도 춘계종합학술대회
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• pp.615-618
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• 2006

본 논문에서는 직접 변환 방식인 six-port의 RF 출력 신호를 검파하고 요구 대역폭에서 입력 주파수 신호에 대한 진폭 및 위상차를 선형적으로 출력하는 광역 power detector를 설계 제작한다. Six-port 출력단에 접속되는 power detector는 높은 정합도를 갖고 반사파로 인한 Six-port 간 위상 불일치를 방지하고, 넓은 대역폭에서 낮은 VSWR을 유지하여야 하는 광역 특성을 갖는 power detector 설계가 필요하다. L-band의 강제 정합 회로와 Ku-band의 정합 회로 그리고 isolator와 정합 회로를 갖는 power detector 회로를 구성하여 요구하는 Six-port 형 power detector 성능을 평가한다.

• 전자공학회논문지SC
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• 제43권2호
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• pp.33-39
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• 2006

본 논문에서는 휴대용 적외선 야시경의 소형 경량화 및 저전력을 위한 전자회로부를 설계하였다. 설계한 전자회로부는 전압자동변환부와 전원공급부로 구성한다. 전압자동변환부는 배터리, 스위치부, 승압부, 전압선택부 등으로 구성한다. 전원공급부는 고광원 감지회로, 배터리 전압감지회로, 적외선 발광회로, 연결감지회로, 공급제어회로 등으로 구성한다. 설계한 전자회로부의 성능은 AN/PVS-14에 비하여 소모전력 및 상온 연속사용 시간에서 우수하였다.

• 조명전기설비학회논문지
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• 제25권2호
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• pp.61-68
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• 2011

The circuit breaker of power distribution board is essential part for the protection of electrical disaster from load short, trouble of power system. For the normal operation of circuit breaker, trip coil of the circuit breaker can cut the mechanical contact of circuit breaker from the detection of power system troubles. This paper presents a design and experimental results of trip coil fault detection system for the real time monitoring of the circuit breaker. The designed system is consisted by the trip coil fault detector which is connected to the each circuit breaker and remote monitoring unit. The trip coil fault detector can detect the impedance and operating voltage of the trip coil, and the detected values are compared with the normal state. And the remote monitoring unit can be connected to the 32 channels of trip coil fault detectors by serial communication. From the designed system, the fault and normal states of the trip coil can be remotely monitored in real time. The designed system is verified by the practical circuit breaker of power distribution board. And the results shows the effectiveness of the designed system.

• 한국군사과학기술학회지
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• 제11권5호
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• pp.5-11
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• 2008

Recently developed radars use the solid-state power amplifier to amplify the RF signal. The stability of RF signal directly depends on that of the electric power. So the stable and reliable electric power should be needed. When the electric power switch is tuned on for the first time in order to operate the radar system, the in-rush current is generated because of the capacitive characteristic. The excess in-rush current breaks the element. Therefore, the analysis about the in-rush current to design the electric power system is necessary. In this paper, modeling and simulation on the whole power system is carried out and the necessity of limiting the in-rush current is verified. After the analysis, the circuit to limit the in-rush current is designed and examined to verify the analysis. The circuit is good enough to limit the in-rush current.

• International journal of advanced smart convergence
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• 제4권1호
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• pp.64-70
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• 2015

This paper proposes fluorescent electronic ballast with high power factor and low line input current harmonics. The system performance can be improved by a charged pump circuit. Details of design and circuit operation are described. The proposed electronic ballast is modified from single-stage half bridge class D electronic ballast by adding capacitor parallel with each power switch and setting the circuit parameter to operate under class DE inverter condition. By using this proposed method the DC bus voltage can be reduced around by 50% compare with conventional class D inverter circuit. Because the power switches are operated at zero voltage switching condition and low dv/dt of class DE switching. The experimental results show that the proper frequency of the prototype is around 50 kHz with input power factor of 0.982, $THD_i$ 10.2% at full load and efficiency of more than 90%.

• Nuclear Engineering and Technology
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• 제55권6호
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• pp.2125-2138
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• 2023

The printed circuit heat exchanger (PCHE) with airfoil fins has the benefits of high compactness, high efficiency and superior heat transfer performance. A novel multi-objective optimization approach is presented to design the airfoil fin PCHE in this paper. Three optimization design variables (the vertical number, the horizontal number and the staggered number) are obtained by means of dimensionless airfoil fin arrangement parameters. And the optimization objective is to maximize the Nusselt number (Nu) and minimize the Fanning friction factor (f). Firstly, in order to investigate the impact of design variables on the thermal-hydraulic performance, a parametric study via the design of experiments is proposed. Subsequently, the relationships between three optimization design variables and two objective functions (Nu and f) are characterized by an improved particle swarm optimization-backpropagation artificial neural network. Finally, a multi-objective optimization is used to construct the Pareto optimal front, in which the non-dominated sorting genetic algorithm II is used. The comprehensive performance is found to be the best when the airfoil fins are completely staggered arrangement. And the best compromise solution based on the TOPSIS method is identified as the optimal solution, which can achieve the requirement of high heat transfer performance and low flow resistance.

• 정보처리학회논문지A
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• 제17A권3호
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• pp.121-126
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• 2010

본 논문에서는 저 전압 스윙 기술을 적용하여 저 전력 회로를 구현하고, 슬립 트랜지스터 (sleep-transistor)를 이용하여 누설전류를 최소화하는 새로운 저 전력 MOS 전류모드 논리회로 (MOS current-mode logic circuit)를 제안하였다. 제안한 회로는 저 전압 스윙 기술을 적용하여 저 전력 특성을 갖도록 설계하였고 고 문턱전압 PMOS 트랜지스터 (high-threshold voltage PMOS transistor)를 슬립 트랜지스터로 사용하여 누설전류를 최소화하였다. 제안한 회로는 $16\;{\times}\;16$ 비트 병렬 곱셈기에 적용하여 타당성을 입증하였다. 이 회로는 슬립모드에서 기존 MOS 전류 모드 논리회로 구조에 비해 대기전력소모가 1/104로 감소하였으며, 정상 동작모드에서 11.7 %의 전력소모 감소효과가 있었으며 전력소모와 지연시간의 곱에서 15.1 %의 성능향상이 있었다. 이 회로는 삼성 $0.18\;{\mu}m$ CMOS 공정을 이용하여 설계하였으며, HSPICE를 통하여 검증하였다.