• 대한전기학회논문지
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• 제31권11호
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• pp.133-140
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• 1982

In recent years, a number of thyristor-controlled shunt compensators have been used in industrial and utility systems for phase balancing, power-factor correction and flicker reduction. This paper describes a simple and basic control scheme and circuits for shunt compensator with a fixed capacitor and thyristor-controlled reactor. Feedforward-control scheme is applied, and compensating currents are computed from the symmetrical components of the disturbed system. A 8 bit microprocessor is used for the computation of the compensating currents as well as for the measurements of the symmetric components. A 3-phase 1 KVA compensator is developed and a good reduction of the unbalance factor of the power source is achieved using it.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1998년도 전력전자학술대회 논문집
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• pp.455-459
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• 1998

In this paper input Series-Output Parallel connected converter configuration for high voltage power conversion applications is proposed and a control method to solve the problems of Input Series-Output Paralles connected converter configuration is introduced. In this configuration snubber circuit or voltage balancing controller that is necessary for the series connection of switching devices is not needed. The effectiveness of this proposed configuration is verified by simulation.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2005년도 전력전자학술대회 논문집
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• pp.298-301
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• 2005

The flying capacitor voltage control of the flying capacitor multi-level inverter (FCMLI) is very important for safe operation. The voltage unbalancing of flying capacitors caused serious problems in safety and reliability of system. In the FCMLI, balancing problem of the flying capacitor has its applications limited. The voltage unbalance is occurred by the difference of each capacitors charging and discharging time applied to FCMLI. This paper investigates and analyzes multi-carrier PWM methods to solve capacitor voltage balancing problem. The Phase-Shift PWM (PSPWM) method that is commonly used, The Modified Carrier-Redistribution PWM (MCRPWM) method and The Saw-Tooth-Rotation PWM (STRPWM) method are discussed and compared with respect to switching state, balancing voltage of capacitors and output waveform. These three PWM methods are analyzed by using a flying capacitor three-level inverter and provided result through simulation. Finally, the harmonics about the output voltages of their methods are compared using the harmonic distortion factor (HDF).

• Journal of Power Electronics
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• 제15권5호
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• pp.1207-1216
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• 2015

In order to suppress the low frequency oscillation of the neutral-point voltage for three-level inverters, this paper proposes a new discontinuous pulse width modulation (DPWM) control method. The conventional sinusoidal pulse width modulation (SPWM) control has no effect on balancing the neutral-point voltage. Based on the basic control principle of DPWM, the relationship between the reference space voltage vector and the neutral-point current is analyzed. The proposed method suppresses the low frequency oscillation of the neutral-point voltage by keeping the switches of a certain phase no switching in one carrier cycle. So the operating time of the positive and negative small vectors is equal. Comparing with the conventional SPWM control method, the proposed DPWM control method suppresses the low frequency oscillation of the neutral-point voltage, decreases the output waveform harmonics, and increases both the output waveform quality and the system efficiency. An experiment has been realized by a neutral-point clamped (NPC) three-level inverter prototype based on STM32F407-CPLD. The experimental results verify the correctness of the theoretical analysis and the effectiveness of the proposed DPWM method.

• Journal of Power Electronics
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• 제12권2호
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• pp.344-356
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• 2012

In recent years, multilevel technology has become an effective and practical solution in the field of moderate and high voltage applications. This paper discusses an APF with a three-level NPC inverter. Obviously, the application of such converter to APFs is hindered by the problem of the voltage unbalance of DC capacitors, which leads to system instability. This paper comprehensively analyzes the theoretical limitations of the neutral-point voltage balancing problem for tracking different harmonic currents utilizing current switching functions from the space vector PWM (SVPWM) point of view. The fluctuation of the neutral point caused by the load currents of certain order harmonic frequency is reported and quantified. Furthermore, this paper presents a close-loop digital control algorithm of the DC voltage for this APF. A PI controller regulates the DC voltage in the outer-loop controller. In the current-loop controller, this paper proposes a simple neutral-point voltage control method. The neutral-point voltage imbalance is restrained by selecting small vectors that will move the neutral-point voltage in the direction opposite the direction of the unbalance. The experiment results illustrate that the performance of the proposed approach is satisfactory.

• 한국정보과학회논문지:시스템및이론
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• 제26권10호
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• pp.1275-1283
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• 1999

본 논문은 CMOS 디지털 회로에서의 전력 소모의 주원인인 신호의 천이중에서 회로의 동작에 직접적인 영향을 미치지 않는 불필요한 신호의 천이인 글리치를 줄이기 위한 효율적인 알고리즘을 제시한다. 제안된 알고리즘은 회로의 지연 증가 없이 게이트 사이징과 버퍼 삽입에 의해 경로 균등(path balancing)을 이룸으로써 글리치를 감소시킨다. 경로 균등화를 위하여 먼저 게이트 사이징을 통해 글리치의 감소와 동시에, 게이트 크기의 최적화를 통해 회로 전체의 캐패시턴스까지 줄일 수 있으며, 게이트 사이징 만으로 경로 균등화가 이루어지지 않을 경우 버퍼 삽입으로 경로 균등화를 이루게 된다. 버퍼 자체에 의한 전력 소모 증가보다 글리치 감소에 의한 전력 감소가 큰 버퍼를 선택하여 삽입한다. 이때 버퍼 삽입에 의한 전력 감소는 다른 버퍼의 삽입 상태에 따라 크게 달라질 수 있어 ILP (Integer Linear Program)를 이용하여 적은 버퍼 삽입으로 전력 감소를 최대화 할 수 있는 저전력 설계 시스템을 구현하였다. 제안된 알고리즘은 LGSynth91 벤치마크 회로에 대한 테스트 결과 회로의 지연 증가 없이 평균적으로 30.4%의 전력 감소를 얻을 수 있었다.Abstract This paper presents an efficient algorithm for reducing glitches caused by spurious transitions in CMOS logic circuits. The proposed algorithm reduces glitches by achieving path balancing through gate sizing and buffer insertion. The gate sizing technique reduces not only glitches but also effective capacitance in the circuit. In the proposed algorithm, the buffers are inserted between the gates where power reduction achieved by glitch reduction is larger than the additional power consumed by the inserted buffers. To determine the location of buffer insertion, ILP (Integer Linear Program) has been employed in the proposed system. The proposed algorithm has been tested on LGSynth91 benchmark circuits. Experimental results show an average of 30.4% power reduction.

• 전기학회논문지
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• 제65권5호
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• pp.760-768
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• 2016

Recently, as one of the policies for carbon free operation method of independent power system replacing diesel generator with renewable energy such as wind power and photovoltaic(PV) system has been presented. Therefore, this paper proposes an operation algorithm and modeling of independent power system by considering CVCF(constant voltage constant frequency) ESS(energy storage system) for constant frequency and voltage, LC(load control) ESS for demand and supply balancing and SVC(static var compensator) for reactive power compensation. From the simulation results based on the various operation scenario, it is confirmed that proposed operation algorithm and modeling may contribute stable operation and carbon free in independent power system.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2019년도 추계학술대회
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• pp.140-141
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• 2019

This paper proposes a series operation algorithm for voltage balancing of modular battery pack charging/discharging system using 3P-CFDAB (3-Phase Current-Fed Dual Active Bridge) converter. By using the proposed algorithm, we can prevent deterioration or loss of a particular module. The algorithm in this paper was verified through PSIM simulation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 하계학술대회 논문집 B
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• pp.1027-1029
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• 2003

STATCOM which is connected the load parrallel with capacitor. is the reactive power compensation device. In this paper. appling the PSIM(POWERSIM) software to STATCOM system. it is simulated the reactive power compensation of balancing load. And, setting a thoroughly going over it's results. we confirmed the function propriety of developed STATCOM system. So, it will be applied the reactive power compensation experimentation of the developing 30kVA STATCOM at our laboratory.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2015년도 전력전자학술대회 논문집
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• pp.393-394
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• 2015

본 논문은 다중 채널 LED(Light Emitting Diode) 구동을 위한 모듈형 전류 평형 회로를 제안한다. 기존 방식은 DC/DC 컨버터단과 다중 채널 LED 전류제어를 위해 각 채널마다 일정한 전류 제어를 하는 LED 드라이버단의 직렬 연결로 구성된다. 하지만 제안회로는 캐패시터의 전하평형원리에 의해 단일 채널 전류 제어로 모든 채널의 LED 전류를 동일하게 제어할 수 있어 DC/DC 컨버터와 LED 드라이버단을 하나로 통합한 단일 전력단 LED 구동회로 구성이 가능하며, 이는 회로구성의 단일화로 소자수 및 사이즈의 소형화가 가능하다. 또한 수동소자만으로 이루어진 모듈형 회로로써 모듈의 추가에 따라 요구되는 LED 채널 수 만큼 다채널 모듈로 확장할 수 있다. 제안회로의 타당성 검증을 위해 1kW급 LED 구동회로에 적용한 시뮬레이션 결과를 제시한다.