• Title/Summary/Keyword: Power Transistors

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Fabrication of Graphene Field-effect Transistors with Uniform Dirac Voltage Close to Zero (균일하고 0 V에 가까운 Dirac 전압을 갖는 그래핀 전계효과 트랜지스터 제작 공정)

  • Park, Honghwi;Choi, Muhan;Park, Hongsik
    • Journal of Sensor Science and Technology
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    • v.27 no.3
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    • pp.204-208
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    • 2018
  • Monolayer graphene grown via chemical vapor deposition (CVD) is recognized as a promising material for sensor applications owing to its extremely large surface-to-volume ratio and outstanding electrical properties, as well as the fact that it can be easily transferred onto arbitrary substrates on a large-scale. However, the Dirac voltage of CVD-graphene devices fabricated with transferred graphene layers typically exhibit positive shifts arising from transfer and photolithography residues on the graphene surface. Furthermore, the Dirac voltage is dependent on the channel lengths because of the effect of metal-graphene contacts. Thus, large and nonuniform Dirac voltage of the transferred graphene is a critical issue in the fabrication of graphene-based sensor devices. In this work, we propose a fabrication process for graphene field-effect transistors with Dirac voltages close to zero. A vacuum annealing process at $300^{\circ}C$ was performed to eliminate the positive shift and channel-length-dependence of the Dirac voltage. In addition, the annealing process improved the carrier mobility of electrons and holes significantly by removing the residues on the graphene layer and reducing the effect of metal-graphene contacts. Uniform and close to zero Dirac voltage is crucial for the uniformity and low-power/voltage operation for sensor applications. Thus, the current study is expected to contribute significantly to the development of graphene-based practical sensor devices.

Electrically Stable Transparent Complementary Inverter with Organic-inorganic Nano-hybrid Dielectrics

  • Oh, Min-Suk;Lee, Ki-Moon;Lee, Kwang-H.;Cha, Sung-Hoon;Lee, Byoung-H.;Sung, Myung-M.;Im, Seong-Il
    • 한국정보디스플레이학회:학술대회논문집
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    • 2008.10a
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    • pp.620-621
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    • 2008
  • Transparent electronics has been one of the key terminologies forecasting the ubiquitous technology era. Several researchers have thus extensively developed transparent oxide-based thin-film transistors (TFTs) on glass and plastic substrates although in general high voltage operating devices have been mainly studied considering transparent display drivers. However, low voltage operating oxide TFTs with transparent electrodes are very necessary if we are aiming at logic circuit applications, for which transparent complementary or one-type channel inverters are required. The most effective and low power consuming inverter should be a form of complementary p-channel and n-channel transistors but real application of those complementary TFT inverters also requires electrical- and even photo-stabilities. Since p-type oxide TFTs have not been developed yet, we previously adopted organic pentacene TFTs for the p-channel while ZnO TFTs were chosen for n-channel on sputter-deposited $AlO_x$ film. As a result, decent inverting behavior was achieved but some electrical gate instability was unavoidable at the ZnO/$AlO_x$ channel interface. Here, considering such gate instability issues we have designed a unique transparent complementary TFT (CTFTs) inverter structure with top n-ZnO channel and bottom p-pentacene channel based on 12 nm-thin nano-oxide/self assembled monolayer laminated dielectric, which has a large dielectric strength comparable to that of thin film amorphous $Al_2O_3$. Our transparent CTFT inverter well operate under 3 V, demonstrating a maximum voltage gain of ~20, good electrical and even photoelectric stabilities. The device transmittance was over 60 % and this type of transparent inverter has never been reported, to the best of our limited knowledge.

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Progress in Novel Oxides for Gate Dielectrics and Surface Passivation of GaN/AlGaN Heterostructure Field Effect Transistors

  • Abernathy, C.R.;Gila, B.P.;Onstine, A.H.;Pearton, S.J.;Kim, Ji-Hyun;Luo, B.;Mehandru, R.;Ren, F.;Gillespie, J.K.;Fitch, R.C.;Seweel, J.;Dettmer, R.;Via, G.D.;Crespo, A.;Jenkins, T.J.;Irokawa, Y.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.3 no.1
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    • pp.13-20
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    • 2003
  • Both MgO and $Sc_2O_3$ are shown to provide low interface state densities (in the $10^{11}{\;}eV^{-1}{\;}cm{\;}^{-2}$ range)on n-and p-GaN, making them useful for gate dielectrics for metal-oxide semiconductor(MOS) devices and also as surface passivation layers to mitigate current collapse in GaN/AlGaN high electron mobility transistors(HEMTs).Clear evidence of inversion has been demonstrated in gate-controlled MOS p-GaN diodes using both types of oxide. Charge pumping measurements on diodes undergoing a high temperature implant activation anneal show a total surface state density of $~3{\;}{\times}{\;}10^{12}{\;}cm^{-2}$. On HEMT structures, both oxides provide effective passivation of surface states and these devices show improved output power. The MgO/GaN structures are also found to be quite radiation-resistant, making them attractive for satellite and terrestrial communication systems requiring a high tolerance to high energy(40MeV) protons.

Effect of Negative Oxygen Ions Accelerated by Self-bias on Amorphous InGaZnO Thin Film Transistors

  • Kim, Du-Hyeon;Yun, Su-Bok;Hong, Mun-Pyo
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.02a
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    • pp.466-468
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    • 2012
  • Amorphous InGaZnO (${\alpha}$-IGZO) thin-film transistors (TFTs) are are very promising due to their potential use in thin film electronics and display drivers [1]. However, the stability of AOS-TFTs under the various stresses has been issued for the practical AOSs applications [2]. Up to now, many researchers have studied to understand the sub-gap density of states (DOS) as the root cause of instability [3]. Nomura et al. reported that these deep defects are located in the surface layer of the ${\alpha}$-IGZO channel [4]. Also, Kim et al. reported that the interfacial traps can be affected by different RF-power during RF magnetron sputtering process [5]. It is well known that these trap states can influence on the performances and stabilities of ${\alpha}$-IGZO TFTs. Nevertheless, it has not been reported how these defect states are created during conventional RF magnetron sputtering. In general, during conventional RF magnetron sputtering process, negative oxygen ions (NOI) can be generated by electron attachment in oxygen atom near target surface and accelerated up to few hundreds eV by self-bias of RF magnetron sputter; the high energy bombardment of NOIs generates bulk defects in oxide thin films [6-10] and can change the defect states of ${\alpha}$-IGZO thin film. In this paper, we have confirmed that the NOIs accelerated by the self-bias were one of the dominant causes of instability in ${\alpha}$-IGZO TFTs when the channel layer was deposited by conventional RF magnetron sputtering system. Finally, we will introduce our novel technology named as Magnetic Field Shielded Sputtering (MFSS) process [9-10] to eliminate the NOI bombardment effects and present how much to be improved the instability of ${\alpha}$-IGZO TFTs by this new deposition method.

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Evaluation of Flexible Complementary Inverters Based on Pentacene and IGZO Thin Film Transistors

  • Kim, D.I.;Hwang, B.U.;Jeon, H.S.;Bae, B.S.;Lee, H.J.;Lee, N.E.
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.02a
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    • pp.154-154
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    • 2012
  • Flexible complementary inverters based on thin-film transistors (TFTs) are important because they have low power consumption and high voltage gain compared to single type circuits. We have manufactured flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The circuits were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. The characteristics of TFTs and inverters were evaluated at different bending radii. The applied strain led to change in voltage transfer characteristics of complementary inverters as well as source-drain saturation current, field effect mobility and threshold voltage of TFTs. The switching threshold voltage of fabricated inverters was decreased with increasing bending radius, which is related to change in parameters of TFTs. Throughout the bending experiments, relationship between circuit performance and TFT characteristics under mechanical deformation could be elucidated.

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Hybrid complementary circuits based on organic/inorganic flexible thin film transistors with PVP/Al2O3 gate dielectrics

  • Kim, D.I.;Seol, Y.G.;Lee, N.E.;Woo, C.H.;Ahn, C.H.;Ch, H.K.
    • Proceedings of the Korean Vacuum Society Conference
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    • 2011.02a
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    • pp.479-479
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    • 2011
  • Flexible inverters based on complementary thin-film transistor (CTFTs) are important because they have low power consumption and other advantages over single type TFT inverters. In addition, integrated CTFTs in flexible electronic circuits on low-cost, large area and mechanically flexible substrates have potentials in various applications such as radio-frequency identification tags (RFIDs), sensors, and backplanes for flexible displays. In this work, we introduce flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The CTFTs were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. Basic electrical characteristics of individual transistors and the whole CTFTs were measured by a semiconductor parameter analyzer (HP4145B, Agilent Technologies) at room temperature in the dark. Performance of those devices then was measured under static and dynamic mechanical deformation. Effects of cyclic bending were also examined. The voltage transfer characteristics (Vout- Vin) and voltage gain (-dVout/dVin) of flexible inverter circuit were analyzed and the effects of mechanical bending will be discussed in detail.

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Design and fabrication of the surface mountable VCO operating at 3V for PCS handset (3V에 동작하는 PCS 단말기용 표면실장형 전압제어 발전기의 설계 및 제작)

  • 염경환
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.21 no.3
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    • pp.784-794
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    • 1996
  • In this papre, the design and the fabrication of the surface mountable voltage controlled oscillator is described for local oscillator in PCS(WACS/TDMA) handset. The VCO employs two silicon bipolar transistors of $f_{gamma}$ of 4 GHz as active devices. These are asembled to form the VCO on the 4 layer PCB of the size $12{\times}10mm$which provides the strip line resonator at the third layer. The fabricated VCO shows tuning rage over 50 MHz, phase noise -100 dBc/Hz at the 100 kHz frequency offset, and 0 dBm output power with the consumption of 22 mA at 3V. It is belived that the size will be more reduced by employing 1005 chip components and that the current consumption will be improved by employing transistors of higher $f_{gamma}$.

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An Organic Electrophosphorescent Device Driven by All-Organic Thin-Film Transistor using Polymeric Gate Insulator

  • Pyo, S.W.;Shim, J.H.;Kim, Y.K.
    • Journal of Information Display
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    • v.4 no.2
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    • pp.1-6
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    • 2003
  • In this paper, we demonstrate that the organic electrophosphorescent device is driven by the organic thin film transistor with spin-coated photoacryl gate insulator. It was found that electrical output characteristics in our organic thin film transistors using the staggered-inverted top-contact structure showed the non-saturated slope in the saturation region and the sub-threshold nonlinearity in the triode region, where we obtained the maximum power luminance that was about 90 $cd/m^2$. Field effect mobility, threshold voltage, and on-off current ratio in 0.45 ${\mu}m$ thick gate dielectric layer were 0.17 $cm^2/Vs$, -7 V, and $10^6$ , respectively. In order to form polyimide as a gate insulator, vapor deposition polymerization process was also introduced instead of spin-coating process, where polyimide film was co-deposited by high-vacuum thermal evaporation from 4,4'-oxydiphthalic anhydride (ODPA) and 4,4'-oxydianiline (ODA) and cured at 150${\sqsubset}$for 1hr. It was also found that field effect mobility, threshold voltage, on-off current ratio, and sub-threshold slope with 0.45 ${\mu}m$ thick gate dielectric films were 0.134 $cm^2/Vs$, -7 V, and $10^6$ A/A, and 1 V/decade, respectively.

Dependence of $O_2$ Plasma Treatment of Cross-Linked PVP Insulator on the Electrical Properties of Organic-Inorganic Thin Film Transistors with ZnO Channel Layer

  • Gong, Su-Cheol;Shin, Ik-Sup;Bang, Suk-Hwan;Kim, Hyun-Chul;Ryu, Sang-Ouk;Jeon, Hyeong-Tag;Park, Hyung-Ho;Yu, Chong-Hee;Chang, Ho-Jung
    • Journal of the Microelectronics and Packaging Society
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    • v.16 no.2
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    • pp.21-25
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    • 2009
  • The organic-inorganic thin film transistors (OITFTs) with ZnO channel layer and the cross-linked PVP (Poly-4-vinylphenol) gate insulator were fabricated on the patterned ITO gate/glass substrate. ZnO channel layer was deposited by using atomic layer deposition (ALD). In order to improve the electrical properties, $O_2$ plasma treatment onto PVP film was introduced and investigated the effect of the plasma treatments on the electrical properties of the OITFTs. The field effect mobility and sub-threshold slope (SS) values of the OITFT decreased slightly from 0.24 to 0.16 $cm^2/V{\cdot}s$ and from 9.7 to 9.2 V/dec, respectively with increasing RF power from 30 to 50 Watt. The $I_{on/off}$ ratio was about $10^3$ for all samples with $O_2$ plasma treatment.

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Investigation of InAs/InGaAs/InP Heterojunction Tunneling Field-Effect Transistors

  • Eun, Hye Rim;Woo, Sung Yun;Lee, Hwan Gi;Yoon, Young Jun;Seo, Jae Hwa;Lee, Jung-Hee;Kim, Jungjoon;Kang, In Man
    • Journal of Electrical Engineering and Technology
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    • v.9 no.5
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    • pp.1654-1659
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    • 2014
  • Tunneling field-effect transistors (TFETs) are very applicable to low standby-power application by their virtues of low off-current ($I_{off}$) and small subthreshold swing (S). However, low on-current ($I_{on}$) of silicon-based TFETs has been pointed out as a drawback. To improve $I_{on}$ of TFET, a gate-all-around (GAA) TFET based on III-V compound semiconductor with InAs/InGaAs/InP multiple-heterojunction structure is proposed and investigated. Its performances have been evaluated with the gallium (Ga) composition (x) for $In_{1-x}Ga_xAs$ in the channel region. According to the simulation results for $I_{on}$, $I_{off}$, S, and on/off current ratio ($I_{on}/I_{off}$), the device adopting $In_{0.53}Ga_{0.47}As$ channel showed the optimum direct-current (DC) performance, as a result of controlling the Ga fraction. By introducing an n-type InGaAs thin layer near the source end, improved DC characteristics and radio-frequency (RF) performances were obtained due to boosted band-to-band (BTB) tunneling efficiency.