• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.575-578
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• 2005

We report on a low-cost V-band wireless transceiver with no use of any local oscillator in the receiver block using a self-heterodyne architecture. V-band Microwave monolithic IC (MMIC) modules were developed to demonstrate the wireless transceiver using coplanar waveguide (CPW) and GaAs PHEMT technologies. The MMIC modules such as the MMIC low noise amplifier (LNA), medium power amplifier (MPA) and the up/down-mixer were installed in the transceiver system. To interface the MMIC chips with the component modules for the transceiver system, CPW-to-waveguide fin-line transition modules of WR-15 type were designed and fabricated. The fabricated LNA modules showed a $S_{21}$ gain of 8.4 dB and a noise figure of 5.6 dB at 58 GHz. The MPA modules exhibited a gain of 6.9 dB and a $P_1$ $_{dB}$ of 5.4 dBm at 58 GHz. The conversion losses of the up-mixer and the down-mixer module were 14.3 dB at a LO power of 15 dBm, and 19.7 dB at a LO power of 0 dBm, respectively. From the measurement of V-band wireless transceiver, a conversion gain of 0.2 dB and a P $_{1dB}$ of 5.2 dBm were obtained in the transmitter block. The receiver block showed a conversion gain of 2.1 dB and a P $_{1dB}$ of -18.6 dBm. The wireless transceiver system demonstrated a successful data transfer within a distance of 5 meters.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.651-659
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• 2010

In this paper, a new six-port direct conversion receiver for high-speed multi-band multi-mode wireless communication system such as software defined radio(SDR) is proposed. The designed receiver is composed of two CMOS four-port BPSK receivers and a dual-band one-stage polyphase filter for quadrature LO signal generation. The four-port BPSK receiver, implemented in 0.18 ${\mu}m$ CMOS technology for the first time in microwave-band, is composed of two active combiners, an active balun, two power detector, and an analog decoder. The proposed polyphase filter adopt type-I architecture, one-stage for reduction of the local oscillator power loss, and LC resonance structure instead of using capacitor for dual-band operation. In order to extent the operation RF bandwidth of the proposed six-port receiver, we include I/Q phase and amplitude calibration scheme in the six-port junction and the power detector. The calibration range of the phase and amplitude mismatch in the proposed calibration scheme is 8 degree and 14 dB, respectively. The validity of the designed six-port receiver is successfully demonstrated by modulating M-QAM, and M-PSK signal with 40 Msps in the two-band of 900 MHz and 2.4 GHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.4
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• pp.443-451
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• 2010

This paper describes a fully integrated CMOS low-IF mobile-TV RF tuner for Band-III T-DMB/DAB applications. All functional blocks such as low noise amplifier, mixers, variable gain amplifiers, channel filter, phase locked loop, voltage controlled oscillator and PLL loop filter are integrated. The gain of LNA can be controlled from -10 dB to +15 dB with 4-step resolutions. This provides a high signal-to-noise ratio and high linearity performance at a certain power level of RF input because LNA has a small gain variance. For further improving the linearity and noise performance we have proposed the RF VGA exploiting Schmoock's technique and the mixer with current bleeding, which injects directly the charges to the transconductance stage. The chip is fabricated in a 0.18 um mixed signal CMOS process. The measured gain range of the receiver is -25~+88 dB, the overall noise figure(NF) is 4.02~5.13 dB over the whole T-DMB band of 174~240 MHz, and the measured IIP3 is +2.3 dBm at low gain mode. The tuner rejects the image signal over maximum 63.4 dB. The power consumption is 54 mW at 1.8 V supply voltage. The chip area is $3.0{\times}2.5mm^2$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.4
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• pp.352-361
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• 2010

In this paper, a compact 20 W block-up-converter for C-band satellite communication is designed and implemented. The designed block up-converter consists of an intermediate frequency circuit, a mixer and local oscillator, a driver amplifier, a solid-state power amplifier, waveguide circuits, and a power supply module. To reduce the size of the block-up-converter, all circuits are assembled within an housing, so its dimension is just $21{\times}14{\times}11cm^3$. Especially, the waveguide filter and microstirp-to-waveguide transition are easily implemented using an housing. Also, to meet spurious and harmonics specification, various compact microstrip filters including an elliptic filter are integrated. Measurement results show that the developed block up-converter has good electrical performances: the output power of 43.7 dBm, the minimum gain of 65 dB, the gain flatness of ${\pm}1.84$, the IMD3 of -35 dBc, and the harmonic level of -105 dBc.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.3
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• pp.210-219
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• 2005

We report on a low-cost V-band wireless transceiver with no use of any local oscillator in the receiver block using a self-heterodyne architecture. V-band millimeter-wave monolithic IC (MMIC) modules were developed to demonstrate the wireless transceiver using coplanar waveguide (CPW) and GaAs PHEMT technologies. The MMIC modules such as the MMIC low noise amplifier (LNA), medium power amplifier (MPA) and the up/down-mixer were installed in the transceiver system. To interface the MMIC chips with the component modules for the transceiver system, CPW-to-waveguide fin-line transition modules of WR-15 type were designed and fabricated. The fabricated LNA modules showed a $S_{21}$ gain of 8.4 dB and a noise figure of 5.6 dB at 58 GHz. The MPA modules exhibited a gain of 6.9 dB and a $P_{1dB}$ of 5.4 dBm at 58 GHz. The conversion losses of the up-mixer and the down-mixer module were 14.3 dB at a LO power of 15 dBm, and 19.7 dB at a LO power of 0 dBm, respectively. From the measurement of V-band wireless transceiver, a conversion gain of 0.2 dB and a $P_{1dB}$ of 5.2 dBm were obtained in the transmitter block. The receiver block showed a conversion gain of 2.1 dB and a $P_{1dB}$ of -18.6 dBm. The wireless transceiver system demonstrated a successful data transfer within a distance of 5 meters.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.71-80
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• 2007

This paper presents a new push-push VCO technique that extracts a second harmonic output signal from a capacitive commonnode in a negativegm oscillator topology. The generation of the $2^{nd}$ harmonics is accounted for by the nonlinear current-voltage characteristic of the emitter-base junction diode causing; 1) significant voltage clipping and 2) different rising and falling time during the switching operation of core transistors. Comparative investigations show the technique is more power efficient in the high-frequency region that a conventional push-push technique using an emitter common node. Prototype 12GHz and 17GHz MMIC VCO were realized in GaInP/GaAs HBT technology. They have shown nominal output power of -4.3dBm and -5dBm, phase noise of -108 dBc/Hz and -110.4 dBc/Hz at 1MHz offset, respectively. The phase noise results are also equivalent to a VCO figure-of-merit of -175.8 dBc/Hz and -184.3 dBc/Hz, while dissipate 25.68mW(10.7mA/2.4V) and 13.14mW(4.38mA/3.0V), respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.3
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• pp.399-405
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• 2011

In this paper, we present the design of Q-band LC VCO and injection locking buffer for 77 GHz automotive radar sensor using 130 nm RF CMOS process. To improve the phase noise characteristic of LC tank, the transmission line is used. The negative resistance by the active device cross-coupled pair of buffer is used for high output power, with or without oscillation of buffer. The measured phase noise is -102 dBc/Hz at 1 MHz offset frequency and tuning range is 34.53~35.07 GHz. The output power is higher than 4.1 dBm over entire tuning range. The fabricated chip size is $510{\times}130\;um^2$. The power consumption of LC VCO is 10.8 mW and injection locking buffer is 50.4 mW from 1.2 V supply.

• ETRI Journal
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• v.26 no.3
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• pp.229-240
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• 2004

This paper reports on our development of a dual-mode transceiver for a CMOS high-rate Bluetooth system-onchip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front-end. It is designed for both the normal-rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high-rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual-path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual-mode system. The transceiver requires none of the external image-rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order onchip filters. The chip is fabricated on a $6.5-mm^{2}$ die using a standard $0.25-{\mu}m$ CMOS technology. Experimental results show an in-band image-rejection ratio of 40 dB, an IIP3 of -5 dBm, and a sensitivity of -77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive ${\pi}/4-diffrential$ quadrature phase-shift keying $({\pi}/4-DQPSK)$ mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5-V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low-cost, multi-mode, high-speed wireless personal area network.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.2
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• pp.111-116
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• 2003

In this paper, a CMOS baseband analog receiver for wireless home network is discussed. It is composed of a Gilbert type mixer, an Elliptic 6th order 1ow pass filter, and a 6-bit A/D converter. The main role of the mixer is generating a mixed analog signal between the 200MHz output signal of CMOS RF stage and the 199MHz local oscillator. After the undesired high frequency component of the mixed signal comes out. Finally, the analog signal is converted into digital code at the 6-bit A/D converter, The proposed receiver is fabricated with 0.25${\mu}{\textrm}{m}$ 1-poly 5-metal CMOS technology, and the chip area is 200${\mu}{\textrm}{m}$ X1400${\mu}{\textrm}{m}$. the receiver consumes 130㎽ at 2.5V power supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.8
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• pp.737-743
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• 2004

A fixed-tuned SIS(Superconductor-Insulator-Superconductor) mixer across 120∼180 GHz band has been developed. This mixer employs an SIS chip fabricated by Nobeyama radio observatory which consists of a series array of 6 Nb/Al-Al$_2$O$_3$/Nb junctions in a microstrip line on a fused quartz substrate. The SIS chip is placed at the center of the half-height waveguide mixer mount to have a good incoming signal coupling over the whole frequency band. No mechanical tuner was used in the SIS mixer and the RF signal and local oscillator power are injected to the mixer via a cooled cross-guide coupler. In order to prevent the IF signal loss, the If output impedance of the SIS mixer was matched to the 50 $\Omega$ input impedance of the IF chain. Measured double sideband noise temperatures of a receiver using the SIS mixer are 32∼131 K over 120∼180 GHz band. The developed SIS mixer is now in use for radio astronomical observations on the TRAO 14 m radio telescope.