• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.2
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• pp.99-108
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• 2018

This paper presents a design study of a solid state power oscillator to replace the conventional magnetron. The operational conditions of a single-stage 300 W LDMOS power amplifier were fully characterized. The power module consisted of two amplifiers connected in parallel. A delay-line feedback loop was designed for self-oscillation. A phase shifter was inserted in the delay-line feedback loop for adjusting the round-trip phase. Experiments performed using the power oscillator showed an output power of 800 W and a DC-RF conversion efficiency of 58 % at 2.327 GHz. The measured results were in good agreement with those predicted by numerical simulations.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.9 no.2
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• pp.171-178
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• 1998

Generally, the output matching circuit has the most influence to the output power of oscillator and existing method for output matching has difficulty for making the optimum output matching circuit because the matching has to be done nearby the infinite impedance area of the Smith Chart. In this paper, it is studied for the output matching circuit of the microwave oscillator to get the maximum output power. The maximum output point can be found by adjusting the position of moving short in the Tuner while the oscillator is operating after connect the 3-dB coupler Tuner to the oscillator without output matching circuit. To design the oscillator for the maximum output power can be done easily with the microstrip line which is realized from the measured S-parameters of Tuner. In compare the oscillator by the existing method with another one by the suggested method in this paper, the first one has 6.45 dBm output power and second one has 9.71 dBm which is 3.26 dBm higher than the first one at the oscillation frequency 1.0338 GHz.

• Journal of electromagnetic engineering and science
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• v.5 no.4
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• pp.204-207
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• 2005

In this paper, PBG structure and feedforward circuit has been used to suppress the phase noise of the oscillator. Microstrip line resonator have low Q, but we can obtain high LO power by feedforward circuit and improve the resonator Q by the PBG, simultaneously. The proposed oscillator which uses PBG and feedforward circuit shows 0${\~}$20 dB phase noise reduction compared to the conventional oscillator. We have obtained -115.8 dBc of phase noise at 100 kHz offset from 2.4 GHz center.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.671-677
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• 2015

A novel phase interpolator (PI) based linear model of multipath ring oscillator (MPRO) is described in this paper. By modeling each delay cell as an ideal summer followed by a single pole RC filter, the oscillation frequency is derived for a 4-stage differential MPRO. It is analytically proved that the oscillation frequency increases with the growth of the forwarding factor ${\alpha}$, which is also confirmed quantitatively through simulation. Based on the proposed model, it is shown that the power to frequency ratio keeps constant as the speed increases. Running at the same speed, a 4-stage MPRO can outperform the corresponding single-stage ring oscillator (SPRO) with 27% power saving, making MPRO with a large forwarding factor ${\alpha}$ an attractive option for lower power applications.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.304-308
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• 2003

A low cost solution employing harmonic oscillation to the frequency synthesizer at 5.8 GHz is proposed. The proposed frequency synthesizer is composed of 2.9GHz PLL chip, 2.9GHz oscillator, and 5.8GHz buffer amplifier. The measured data shows a frequency tuning range of 290MHz, ranging from 5.65 to 5.94GHz, about 0.5dBm of output power, and a phase noise of -107.67 dBc/Hz at the 100kHz offset frequency. All spurious signals including fundamental oscillation power (2.9GHz) are suppressed at least 15dBc than the desired second harmonic signal.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.12
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• pp.1700-1705
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• 2013

A second harmonic millimeter wave oscillator utilizing sub-harmonic injection-synchronization is presented. A 8.7GHz oscillator with MES-FET is designed, and is driven as a harmonic output oscillator at 17.4GHz by means of sub-harmonic injection-synchronization. The oscillator operates as a multiplier as well as a oscillator in this scheme. Adopting this method, a high sable, high frequency millimeter wave source is obtainable even though self-oscillating frequency of an oscillator is relatively low. The range of injection-synchronization is about 26MHz, and is proportional to the input sub-harmonic power. The spectrum analysis of the 2nd harmonic output frequency shows remarkably decreased the phase noise level.

• Journal of electromagnetic engineering and science
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• v.15 no.4
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• pp.232-238
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• 2015

This work describes the development of a D-band (110-170 GHz) signal source based on a SiGe BiCMOS technology. This D-band signal source consists of a V-band (50-75 GHz) oscillator, a V-band amplifier, and a D-band frequency doubler. The V-band signal from the oscillator is amplified for power boost, and then the frequency is doubled for D-band signal generation. The V-band oscillator showed an output power of 2.7 dBm at 67.3 GHz. Including a buffer stage, it had a DC power consumption of 145 mW. The peak gain of the V-band amplifier was 10.9 dB, which was achieved at 64.0 GHz and consumed 110 mW of DC power. The active frequency doubler consumed 60 mW for D-band signal generation. The integrated D-band source exhibited a measured output oscillation frequency of 133.2 GHz with an output power of 3.1 dBm and a phase noise of -107.2 dBc/Hz at 10 MHz offset. The chip size is $900{\times}1,890{\mu}m^2$, including RF and DC pads.

• Transactions on Electrical and Electronic Materials
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• v.18 no.4
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• pp.185-189
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• 2017

This paper proposes a low power frequency divider for an integrated CMOS phase-locked loop (PLL). An injection-locked frequency divider (ILFD) was designed, along with a current-mode logic (CML) frequency divider in order to obtain a broadband and high-frequency operation. A ring oscillator was designed to operate at 1.2 GHz, and the ILFD was used to divide the frequency of its input signal by two. The structure of the ILFD is similar to that of the ring oscillator in order to ensure the frequency alignment between the oscillator and the ILFD. The CML frequency divider was used as the second stage of the divider. The proposed frequency divider was applied in a conventional PLL design, using a 0.18 ${\mu}m$ CMOS process. Simulation shows that the proposed divide-by-two ILFD and the divide-by-eight CML frequency dividers operated as expected for an input frequency of 1.2 GHz, with a power consumption of 30 mW.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.298-302
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• 2006

Models for the phase noise and jitter of the ring oscillator with the power supply noise are suggested and verified by simulations. The power supply noise is converted into the phase-noise by the narrow band phase modulation. The phase-noise appears as sideband frequencies apart from the center frequency of the ring oscillator as much as the frequency of the power supply noise. A jitter model describing the linear relation of jitter with the amplitude of the power supply noise is suggested and verified by simulation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.2
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• pp.119-126
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• 2003

In this paper, a cylindrical cavity resonator oscillator with high Q factor is designed and fabricated to improve the phase noise characteristic. A cavity resonator is coupled to oscillating circuit using aperture hole. Measured results show that the cylindrical cavity resonator oscillator (CRO) for Ku-band has less phase noise than the dielectric resonator oscillator (DRO) with the same oscillating circuit. It has output power of +3.92 dBm at the center frequency 13.4015250 GHz and phase noise of -109 dBc/Hz at 100 kHz offset.