• Title/Summary/Keyword: Power Number

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Digital Sequence CPLD Technology Mapping Algorithm

  • Youn, Choong-Mo
    • Journal of information and communication convergence engineering
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    • v.5 no.2
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    • pp.131-135
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    • 2007
  • In this paper, The proposed algorithm consists of three steps. In the first step, TD(Transition Density) calculation has to be performed. a CLB-based CPLD low-power technology mapping algorithm considered a Trade-off is proposed. To perform low-power technology mapping for CPLDs, a given Boolean network has to be represented in a DAG. Total power consumption is obtained by calculating the switching activity of each node in a DAG. In the second step, the feasible clusters are generated by considering the following conditions: the number of inputs and outputs, the number of OR terms for CLB within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low-power technology mapping based on the CLBs packs the feasible clusters. The proposed algorithm is examined using SIS benchmarks. When the number of OR terms is five, the experiment results show that power consumption is reduced by 30.73% compared with TEMPLA, and by 17.11 % compared with PLA mapping.

Development of Monitor Positioning Algorithm considering Power System Topology and Distributed Generation (분산전원과 토폴로지를 고려한 배전계통에서의 전기품질 모니터 위치 선정 기법)

  • Moon, Dae-Seong;Kim, Yun-Seong;Won, Dong-Jun
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.57 no.10
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    • pp.1744-1751
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    • 2008
  • This paper presents a monitor positioning algorithm to identify the power quality event source in the distribution system with distributed generations. This algorithm determines the appropriate number of monitors and their locations considering power system topology together with distributed generation. This paper summarizes the guidelines of monitor positioning into five principles and defines the weighting factors according to the principles. To evaluate the adequacy of monitor positioning results, ambiguity indices considering monitor location and system topology are proposed. The optimal number and locations of monitors are determined from optimization routine using the weighting factors and the monitor positioning results are evaluated in terms of ambiguity indices. The algorithm is applied to IEEE 13 bus test feeder and suggests the optimal number and locations of power quality monitors. The proposed approach can realize the expert's knowledge on monitor positioning into a sophisticated automatic computing algorithm.

The Low Power Algorithm using a Feasible Clustert Generation Method considered Glitch (글리치를 고려한 매핑가능 클러스터 생성 방법을 이용한 저전력 알고리즘)

  • Kim, Jaejin
    • Journal of Korea Society of Digital Industry and Information Management
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    • v.12 no.2
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    • pp.7-14
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    • 2016
  • In this paper presents a low power algorithm using a feasible cluster generation method considered glitch. The proposed algorithm is a method for reducing power consumption of a given circuit. The algorithm consists of a feasible cluster generation process and glitches removal process. So that glitches are not generated for the node to which the switching operation occurs most frequently in order to reduce the power consumption is a method for generating a feasible cluster. A feasible cluster generation process consisted of a node value set, dividing the node, the node aligned with the feasible cluster generation. A feasible cluster generation procedure is produced from the highest number of nodes in the output. When exceeding the number of OR-terms of the inputs of the selected node CLB prevents the signal path is varied by the evenly divided. If there are nodes with the same number of outputs selected by the first highest number of nodes in the input produces a feasible cluster. Glitch removal process removes glitches through the path balancing in the same manner as [5]. Experimental results were compared with the proposed algorithm [5]. Number of blocks has been increased by 5%, the power consumption was reduced by 3%.

Level Number Effect on Performance of a Novel Series Active Power Filter Based on Multilevel Inverter

  • Karaarslan, Korhan;Arifoglu, Birol;Beser, Ersoy;Camur, Sabri
    • Journal of Electrical Engineering and Technology
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    • v.13 no.2
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    • pp.711-721
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    • 2018
  • This paper presents a single-phase asymmetric half-bridge cascaded multilevel inverter based series active power filter (SAPF) for harmonic voltage compensation. The effect of level number on performance of the proposed SAPF is examined in terms of total harmonic distortion (THD) and system efficiency. Besides, the relationship between the level number and the number of switching device are compared with the other multilevel inverter topologies used in APF applications. The paper is also aimed to demonstrate the capability of the SAPF for compensating harmonic voltages alone, without using a passive power filter (PPF). To obtain the required output voltage, a new switching algorithm is developed. The proposed SAPF with levels of 7, 15 and 31 is used in both simulation and experimental studies and the harmonic voltages of the load connected to the point of common coupling (PCC) is compensated under two different loading conditions. Furthermore, very high system efficiency values such as 98.74% and 96.84% are measured in the experimental studies and all THD values are brought into compliance with the IEEE-519 Standard. As a result, by increasing the level number of the inverter, lower THD values can be obtained even under high harmonic distortion levels while system efficiency almost remains the same.

a- Si:H TFT Level Shifter with Reduced Number of Power

  • Jeong, Nam-Hyun;Chun, Young-Tea;Kim, Jung-Woo;Bae, Byung-Seong
    • 한국정보디스플레이학회:학술대회논문집
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    • 2008.10a
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    • pp.20-23
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    • 2008
  • We proposed a-Si:H TFT (hydrogenated amorphous silicon thin film transistor) level shifter which reduced number of power sources. To reduce the number of power sources from four to two, modified bootstrapped inverter was used for the level shifter. The shift register was verified by PSPICE circuit simulation and fabricated. The fabricated level shifter successfully shifted low input (0 to 5 V) to high level output (-7 to 23 V).

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Low-Power Decimation Filter Using Approximate Processing with Control of Error in CSD Representation (CSD 표현의 오차를 이용한 Approximate Processing과 이를 이용한 저전력 Decimation Filter의 설계)

  • 양영모;김영우;김수원
    • Proceedings of the IEEK Conference
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    • 1999.11a
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    • pp.236-239
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    • 1999
  • This paper describes a low-power design of decimation filter. To reduce power consumption, an approximate processing method which controls the error in canonic signed digit(CSD) coefficients is proposed. The CSD representation reduces the number of operations by representing multiplications with add and shift operations. The proposed method further reduces the number of operations by controlling the error of CSD coefficient. Processor type architecture is used to implement the proposed method. Simulation result shows that the number of operations is reduced to 56%, 35% and 10% at each approximated filter level.

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The Traffic Analysis of DCS Network with Different Mode number (DCS통신망의 노드 변화에 따른 트래픽 분석)

  • Jo, H.S.;Oh, E.S.;Song, S.I.
    • Proceedings of the KIEE Conference
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    • 2003.07d
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    • pp.2121-2123
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    • 2003
  • Distributed Control Systems(DCS) arc used in a wide range of process applications such as power plants. This paper presents calculated network capacity of a DCS that developed for nuclear power plant. The network hierarchies are 3 layed of information network, control network and field network. The assumed total node number of maximum DCS network is 64. Worst case network utilization of the DCS is simulated and analyzed.

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A Study on The Prediction of Number of Failures using Markov Chain and Fault Data (마코프 체인과 고장데이터를 이용한 고장건수 예측에 관한 연구)

  • Lee, Hee-Tae;Kim, Jae-Chul
    • Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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    • 2008.10a
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    • pp.363-366
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    • 2008
  • It was accomplished that failure analysis not only failure numbers but also power system components every years. and these informations help power system operation considerably. power system equipment were occurred a break down by natural phenomenon and aging but it was not able to predict this failure number. But many papers and technical repots study for each equipment failure rate and reliability evaluation methods. so this paper show a failure number prediction whole power system component using Markov theory not each component failure probability. the result present a next month system failure number prediction.

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Explicit Design of Uniformly Rough Pipe

  • Yoo, Dong-Hoon
    • Korean Journal of Hydrosciences
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    • v.7
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    • pp.107-124
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    • 1996
  • Pipe design normally requires pump power, discharge or pipe diameter for each condition given. Due to several investigators the pipe friction factor con now be estimated by explicit way for a wide range of flow condition. In various problems of pipe design, however, the flow condition cannot be pre-determined even for a uniformly rough pipe. In these cases a lot of iterations are often required to have an accurate solution with ordinary approach. This paper presents the direct computation method of discharge and pipe diameter without any iteration process. Introducing the power law of friction factor, various non-dimensional physical numbers are derived such as power-diameter number, power-discharge number, diameter-slope number and discharge-slope number. One of the physical numbers concerned with discharge or pipe diameter can be related to a combination of the other in an explicit way.

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Competition between Online Stock Message Boards in Predictive Power: Focused on Multiple Online Stock Message Boards

  • Kim, Hyun Mo;Park, Jae Hong
    • Asia pacific journal of information systems
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    • v.26 no.4
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    • pp.526-541
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    • 2016
  • This research aims to examine the predictive power of multiple online stock message boards, namely, NAVER Finance and PAXNET, which are the most popular stock message boards in South Korea, in stock market activities. If predictive power exists, we then compare the predictive power of multiple online stock message boards. To accomplish the research purpose, we constructed a panel data set with close price, volatility, Spell out acronyms at first mention.PER, and number of posts in 40 companies in three months, and conducted a panel vector auto-regression analysis. The analysis results showed that the number of posts could predict stock market activities. In NAVER Finance, previous number of posts positively influenced volatility on the day. In PAXNET, previous number of posts positively influenced close price, volatility, and PER on the day. Second, we confirmed a difference in the prediction power for stock market activities between multiple online stock message boards. This research is limited by the fact that it only considered 40 companies and three stock market activities. Nevertheless, we found correlation between online stock message board and stock market activities and provided practical implications. We suggest that investors need to focus on specific online message boards to find interesting stock market activities.