• Journal of Korea Society of Digital Industry and Information Management
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• v.10 no.1
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• pp.1-6
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• 2014

In this paper, we propose a CPLD low power algorithm considering the structure. The proposed algorithm is implemented CPLD circuit FC(Feasible Cluster) for generating a problem occurs when the node being split to overcome the area and power consumption can reduce the algorithm. CPLD to configure and limitations of the LE is that the number of OR-terms. FC consists of an OR node is divided into mainly as a way to reduce the power consumption with the highest number of output nodes is divided into a top priority. The highest number of output nodes with the highest number of switching nodes become a cut-point. Division of the node is the number of OR-terms of the number of OR-terms LE is greater than adding the input and output of the inverter converts the AND. Reduce the level, power consumption and area. The proposed algorithm to MCNC logic circuits by applying a synthetic benchmark experimental results of 13% compared to the number of logical blocks decreased. 8% of the power consumption results in a reduced efficiency of the algorithm represented been demonstrated.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.7 no.2
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• pp.184-201
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• 2013

In this paper, we study the problem of designing the power and number of cooperative node (CN) in the cooperation phase to maximize the average throughput for secondary user (SU), under the constraint of the total cooperation and transmission power. We first investigate the scheme of cooperative spectrum sensing without a separated control channel. Then, we prove that there indeed exist an optimal CN power when the number of CNs is fixed and an optimal CN number when CN power is fixed. The case without the constraints of the power and number of CN is also studied. Finally, numerical results demonstrate the characteristics and existences of optimal CN power and number. Meanwhile, Monte Carlo simulation results match to the theoretical results well.

• Current Photovoltaic Research
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• v.11 no.1
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• pp.34-37
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• 2023

Solar energy had become the main energy industry of renewable energy along with hydroelectric power generation. One of the technologies that contributed to the popularization of photovoltaic power and the decrease in the unit price of photovoltaic modules was the large-area solar cell. However, as the area increased, the light receiving area increased and the current value increased accordingly. Since power loss occurs when the current value was large, the number of busbar was increased to increase the current collection rate, and a technology to lower the current value through half-cutting was developed. The bus bar of the solar cell served as a passage through which the generated current was transmitted. This was because when the number of busbar decreases, the moving distance of electrons increased, so the amount of power generation decreases and when it increases, shadows occured. An important aspect of the electrode design was the optimal balance of these busbars and number of fingers. Therefore, in this study, the characteristics of the solar cell according to the number of front bus bars of the large-area solar cell were simulated using Griddler 2,5 pro. After selecting the number of busbar with the best characteristics, the difference was compared by varying the number of fingers and a better direction for the number of cutting was presented.

• Journal of Digital Contents Society
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• v.14 no.1
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• pp.59-64
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• 2013

In this paper, we proposed low power algorithm for a task. The task means the inside of a necessary processor and external resources to work accomplishment of a system. Each task analyzes a life time and a number of called for implement a low power circuit. First of all, reduce power consumption of a task have maximum power consumption for low power circuit implementation. Therefore, first selecting a task had maximum power consumption. The task had a maximum power consumption ranking consider a life time and a number of called for each task. While a life time of task is long, top priority ranking to decrease power consumption to the task that the number of call generates the power consumption how a disguise is large in case of a lot of task becomes. Frequency decision to have minimum power consumption, and decrease power consumption all the circuit by a change of frequency of the task which the minimum task that a wasting past record is the maximum becomes. Also, keep continuously minimum power consumption, with every effort task until last life time in opening life time, and decrease gets total power consumption. Experiments results show reduction in the power consumption by 5.43% comparing with that [7] algorithm.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.6
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• pp.2581-2594
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• 2018

The microcell terrain is the most common wireless network terrain in our life. In order to solve wireless network optimization of weak coverage in the microcell terrain, improve call quality and reduce the cost of the premise, power amplifiers in base stations should be adjusted according to user volume. In this paper, characteristics of microcell topography are obtained after analysis. According to the topography characteristics of different microcells, changes in the number of users at different times have been estimated, meanwhile, the number of scatter users are also obtained by monitoring the PCCPCH RSCP and other parameters. Then B-Spline interpolation method has been applied to scatter users to obtain the continuous relationship between the number of users and time. On this basis, power amplification can be chosen according to changes in the number of users. The methods adopted by this paper are also applied in the engineering practice, sampling and interpolation are used to obtain the number of users at all times, so that the power amplification can be adjusted by the number of users in a microcell. Such a method is able to optimize wireless network and achieve a goal of expanding the area of base stations, reduce call drop rate and increase capacity.

• Journal of information and communication convergence engineering
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• v.5 no.1
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• pp.59-63
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• 2007

In this paper, a CLB-based CPLD low-power technology mapping algorithm considered a Trade-off is proposed. To perform low-power technology mapping for CPLDs, a given Boolean network has to be represented in a DAG. The proposed algorithm consists of three steps. In the first step, TD(Transition Density) calculation has to be performed. Total power consumption is obtained by calculating the switching activity of each node in a DAG. In the second step, the feasible clusters are generated by considering the following conditions: the number of inputs and outputs, the number of OR terms for CLB within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low-power technology mapping based on the CLBs packs the feasible clusters. The proposed algorithm is examined using SIS benchmarks. When the number of OR terms is five, the experiment results show that power consumption is reduced by 30.73% compared with TEMPLA, and by 17.11 % compared with PLA mapping.

• Journal of Power Electronics
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• v.15 no.4
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• pp.951-963
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• 2015

In this paper, a new symmetric multilevel inverter is proposed. A simple structure for the cascaded multilevel inverter topology is also proposed, which produces a high number of levels with the application of few power electronic devices. The symmetric multilevel inverter can generate 2n+1 levels with a reduced number of power switches. The basic unit is composed of a single and double source unit (SDS-unit). The application of this SDS-unit is for reducing the number of power electronic components like insulated gate bipolar transistors, freewheeling diodes, gate driver circuits, dc voltage sources, and blocked voltages by switches. Various new algorithms are recommended to determine the magnitude of dc sources in a cascaded structure. Furthermore, the proposed topology is optimized for different goals. The proposed cascaded structure is compared with other similar topologies. For verifying the performance of the proposed basic symmetric and cascaded structure, results from a computer-based MATLAB/Simulink simulation and from experimental hardware are also discussed.

• 한국신재생에너지학회:학술대회논문집
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• 2008.05a
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• pp.270-273
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• 2008

The integrated power system combining a tidal power plant and two ocean current power parks is suggested. It is characterized by the set up of an ocean current power park in the lake side by installing a number of ocean current turbines generating electricity by using sea water flow discharged into the lake side from the turbine generator of a tidal power plant and an ocean current power park in the sea side by installing a number of ocean current turbines generating electricity by using sea water flow exiting into the sea side through the sluice gate from the lake side. The vision of the integrated power system is demonstrated by the simple theory and simulation results of the SIWHA Tidal Power Plant. And it is shown that the newly proposed integrated power system combining tidal power and ocean current power can produce very high economical benefits.

• Journal of the Korean Society of Mechanical Technology
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• v.13 no.2
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• pp.85-91
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• 2011

Computational results with pseudoplastic fluid flows for fully developed non-Newtonian laminar flows have been obtained. Those consist of the product of friction factor and Modified Reynolds number and Nusselt numbers with respect to the shear rate parameter in an annular pipe. The numerical results of the product of friction factor and Reynolds numbers and the Nusselt numbers for both Newtonian region and the power law region were compared with previously published asymptotic results, respectively. In the present calculations, the product of friction factor and Newtonian Reynolds numbers for pseudoplastic fluid at power law region in annular pipe is 180% less than that for Newtonian fluid. For power law fluids with different power law flow indices, the difference of the product of friction factor and power law Reynolds number between previous and the present results at the power law region is within 0.20%. The solutions also show the effect of the shear rate parameter on the Nusselt number and about 11% increase of Nusselt number at the power region.

• Journal of Electrical Engineering and Technology
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• v.8 no.6
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• pp.1328-1336
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• 2013

Nowadays multilevel inverters are developing generally due to reduced voltage stress on power switches and low total harmonic distortion (THD) in output voltage. However, for increasing the output voltage levels the number of circuit devices are increased and it results in increasing the cost of converter. In this paper, a novel multilevel inverter is proposed. The suggested topology uses less number of power switches and related gate drive circuits to generate the same level in output voltage with comparison to traditional cascaded multilevel inverter. With the proposed topology all levels in output voltage can be realized. As an illustration, a symmetric 13-level and asymmetric 29-level proposed inverters have been simulated and implemented. The total peak inverse (PIV) and power losses of presented inverter are calculated and compared with conventional cascaded multilevel inverter. The presented analyses show that the power losses in the suggested multilevel inverter are less than the traditional inverters. Presented simulation and experimental results demonstrate the feasibility and applicability of the proposed inverter to obtain the maximum number of levels with less number of switches.