• Transactions on Electrical and Electronic Materials
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• v.14 no.1
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• pp.28-31
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• 2013

A volcano shaped gated Si-FEA (silicon field emitter array) was simply fabricated using sputtering as a gate electrode deposition and lift-off for the removal of the oxide mask, respectively. Due to the limited step coverage of well-controlled sputtering and the high aspect ratio in Si dry etch caused by high RF power, it was possible to obtain Si FEAs with a stable volcano shaped gate structure and to realize the restriction of gate leakage current in field emission characteristics. For 100 tip arrays and 625 tip arrays, gate leakage currents were restricted to less than 1% of the anode current in spite of the volcano-shaped gate structure. It was also possible to keep the emitters stable without any failure between the Si cathode and gate electrode in field emission for a long time.

• Proceedings of the KWS Conference
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• 2006.10a
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• pp.190-192
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• 2006

The 3-dimensional(3D) chip stacking technology is one of the leading technologies to realize a high density and high performance system in package(SIP). It could be found that it is the advanced process of through-hole via formation with the minimum damaged on the Si-wafer. Laser ablation is very effective method to penetrate through hole on the Si-wafer because it has the advantage that formed under $100{\mu}m$ diameter through-hole via without using a mask. In this paper, we studied the optimum method for a formation of through-hole via using femto-second laser heat sources. Furthermore, the processing parameters of the specimens were several conditions such as power of output, pulse repetition rate as well as irradiation method and time. And also the through-hole via form could be investigated and analyzed by microscope and analyzer.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.1
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• pp.39-43
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• 2001

$SiC_{x}N$_{y}$ film is deposited by electron cyclotron resonance plasma chemical vapor deposition system using $SiH_4$(5% in Ar), $CH_4$ and $N_2$. Ternary phase $SiC_{x}N$_{y}$ thin film deposited at the microwave power of 600 W and substrate temperature of 700 contains considerable amount of strong C-N bonds. Change in $CH_4$flow rate can effectively control the residual film stress, and typical surface roughness of 34.6 (rms) was obtained. Extreme]y high hardness (3952 Hv) and optical transmittance (95% at 633 nm) was achieved, which is suitable for a LIGA mask membrane application.

• ETRI Journal
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• v.20 no.1
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• pp.37-45
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• 1998

Reduced surface field lateral double-diffused MOS transistor for the driving circuits of plasma display panel and field emission display in the 120V region have been integrated for the first time into a low-voltage $1.2{\mu}m$ analog CMOS process using p-type bulk silicon. This method of integration provides an excellent way of achieving both high power and low voltage functions on the same chip; it reduces the number of mask layers double-diffused MOS transistor with a drift length of $6.0{\mu}m$ and a breakdown voltage greater than 150V was self-isolated to the low voltage CMOS ICs. The measured specific on-resistance of the lateral double-diffused MOS in $4.8m{\Omega}{\cdot}cm^2$ at a gate voltage of 5V.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.06a
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• pp.612-615
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• 2003

Maskless laser patterning process is developed using 3rd harmonic Diode Pumped Solid State Laser with near visible wavelength of 355 nm. Photo-sensitive curable polymer is irradiated by UV laser and developed using polymer solvent to obtain quasi-3D patterns. We performed basic experiments for the various process conditions such as laser power, writing speed, laser focus, and polymer optical property to gain the optimal conditions. Experimentally, the patterns of trapezoidal shape were manufactured into dimension of 8${\mu}{\textrm}{m}$ width and 5.4${\mu}{\textrm}{m}$ height. This process could be applied to fabricate a single mode waveguide without expensive mask projection method.

• Laser Solutions
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• v.10 no.4
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• pp.18-22
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• 2007

In this paper, we suggested the femtosecond laser processing using the mask which makes Gaussian spatial beam distribution to a normalized distribution by Fresenel diffraction. Holography pattern of the size of $320{\times}320{\mu}m^2$ on the Cr thin film on glass substrate with a pixel size of $5{\times}5{\mu}m^2$ was fabricated according to the pattern generated by the iterative Fourier transform algorithm(IFTA) algorithm. We analysed the damage threshold with an assumption the power distribution as Gaussian profile as 45 $mJ/cm^2$. The regenerated image of letters through the diffractive pattern was well recognized at the screen.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.10
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• pp.853-858
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• 2003

In this study, a new simplified technology for fabricating high density trench gate DMOSFETs using only three mask layers and TEOS/nitride spacer is proposed. Due to the reduced masking steps and self-aligned process, this technique can afford to fabricate DMOSFETs with high cell density up to 100 Mcell/inch$^2$ and cost-effective production. The resulting unit cell pitch was 2.3∼2.4${\mu}$m. The fabricated device exhibited a excellent specific on-resistance characteristic of 0.36m$\Omega$. cm$^2$ with a breakdown voltage of 42V. Moreover, time to breakdown of gate oxide was remarkably increased by the hydrogen annealing after trench etching.

• Journal of the Korean Society for Precision Engineering
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• v.20 no.12
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• pp.42-47
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• 2003

The laser direct writing method has some advantages of being maskless, allowing rapid and inexpensive prototyping in comparison to conventional mask-based photolithography. In general, there are two kinds of laser direct writing methods such as the laser ablation method and the laser polymerization method. The laser polymerization method was studied fur manufacturing waveguide in this paper. It is important to reduce line width for image mode waveguides, so some investigations will be carried out in various conditions of process parameters such as laser power, writing speed, focusing height and optical properties of polymer. Experimentally, the optical waveguide was manufactured trapezoid shape. Through SEM the waveguide was 20 ${\mu}{\textrm}{m}$ width and 7.4 ${\mu}{\textrm}{m}$ height.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.4
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• pp.136-141
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• 1996

In this paper, a new CMOS on-chip current reference circit for memory, operational amplifiers, comparators, and data converters is proposed. The reference current is almost independent of temeprature and power-supply variations. In the proposed circuit, the current component with a positive temeprature coefficient cancels that with a negative temperature coefficient each other. While conventional curretn and voltage reference circuits require BiCMOS or bipolar process, the presented circuit can be integrated on a single chip with other digiral and analog circits using a standard CMOS process and an extra mask is not needed. The prototype is fabricated employing th esamsung 1.0um p-well double-poly double-metal CMOS process and the chip area is 300um${\times}$135 um. The proposed reference current circuit shows the temperature coefficient of 380 ppm/.deg. C with the temperature changes form 30$^{\circ}C$ to 80$^{\circ}C$, and the output variation of $\pm$ 1.4% with the supply voltage changes from 4.5 V to 5.5 V.

• Information and Communications Magazine
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• v.24 no.3
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• pp.76-86
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• 2007

This paper describes the RF performance issues of UE RF Transceiver for W-CDMA system based on 3GPP specifications. the parameters of transmitter and receiver are derived from the viewpoint of RF performance. In order for UE to achieve high performance, the transceiver performance requirements such as ACIR, EVM, Peak Code Domain Error, spectrum emission mask, frequency error stability and TX power control dynamic range for transmitter and reference sensitivity level, blocking characteristics, noise figure, ACS, linearity, AGC dynamic range for receiver are considered. On the basis of the required parameters, the UE RF transceiver is designed and then implemented. The evaluation of RF performance is accomplished through practical test scenarios.