• The Transactions of the Korean Institute of Electrical Engineers P
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• v.65 no.4
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• pp.255-261
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• 2016

Korean Power System are operating a load shedding system to prevent voltage instability phenomenon caused by severe line contingencies. In order to apply the load shedding scheme should be selected a location, amount, delay time. Current load shedding system is load shedding amount that has been calculated in the steady-state analysis to load shed the total amount in first level, load shedding amount calculated in advance, it is possible to perform an unnecessary load shedding. In this paper, set a multi-level load shedding control strategy step-by-step selection of load shedding amount for the prevention of excessive load shedding. In addition, through a voltage resilience analysis of the power system by applying motor load ratio and sensitivity parameter to selection the multi level load shedding ratio and delay time. For this reason, to take advantage of the limit data of interchange power, by utilizing interface power flow data to set a multi-level load shedding control strategy for the stabilization of the Korean Power System.

• Journal of Power Electronics
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• v.9 no.4
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• pp.593-603
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• 2009

This paper proposes and describes the design and operational principles of a three-phase three-level nine switch voltage source inverter. The proposed topology consists of three bi-directional switches inserted between the source and the full-bridge power switches of the classical three-phase inverter. As a result, a three-level output voltage waveform and a significant suppression of load harmonics contents are obtained at the inverter output. The harmonics content of the proposed multilevel inverter can be reduced by half compared with two-level inverters. A Fourier analysis of the output waveform is performed and the design is optimized to obtain the minimum total harmonic distortion. The full-bridge power switches of the classical three-phase inverter operate at the line frequency of 50Hz, while the auxiliary circuit switches operate at twice the line frequency. To validate the proposed topology, both simulation and analysis have been performed. In addition, a prototype has been designed, implemented and tested. Selected simulation and experimental results have been provided.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.2584-2586
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• 2000

A drum level control is one of the most important control systems in thermal power plant. The control objective of drum level of boiler in thermal power plant is to maintain drum level at constant set-point regardless of disturbance such as main steam flow. The implemented drum level controller is the cascade PI controller. The important factor in drum level controller is the parameters of two PI controllers. The tuning of PI controller parameter is tedious and time-consuming job. In this paper, the relay feedback Ziegler - Nichols tuning method extended to auto-tune cascade PI drum level controller. Finally, the simulation result using boiler model in Power Plant shows the validity of auto-tuned cascade PI controller.

• The Journal of the Korea Contents Association
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• v.12 no.7
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• pp.11-20
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• 2012

This paper presents new instruction-level power model for an asynchronous processor, A8051. Even though the proposed model estimates power consumption as instruction level, this model reflects the behavioral features of asynchronous pipeline during the program is executed. Thus, it can effectively enhance the accuracy of power model for an asynchronous embedded processor without significant complexity of power model as well as the increase of simulation time. The proposed power model is based on the implementation of A8051 to reflect the characteristics of power consumption in A8051. The simulation results of the proposed model is compared with that of gate-level synthesized A8051. The proposed power model shows the accuracy of 94% and the simulation time for estimation the power consumption was reduced to 1,600 times.

• Proceedings of the KIPE Conference
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• 1996.06a
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• pp.126-129
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• 1996

This paper study on the control method of 3-level converter. The control of converter is composed of active power control for controlling a output voltage and of reactive power control for high power factor drives. And also, output central voltage is controlled by sensing a each condensor voltage of bank connected the part of dc.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.2
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• pp.268-275
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• 2015

This paper proposes a method of switching to improve power loss for the single-phase three-level NPC inverter. The conventional switching methods, which are called as the bipolar and unipolar switching methods, are used for single phase inverters using three-level topology. However, these switching method have disadvantage in the power loss. Because all of the switch are operated. To reduce the power loss of the three-level NPC inverter, clamp switching method is introduced in this paper. This way, one of the lag is fixed that switching loss is reduced. This paper analyzes and compares power losses of unipolar method and clamp method. The validity of the power loss analysis is verified through the simulation and experimental results.

• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.2
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• pp.127-132
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• 2020

In this study, single-phase and three-level boost converters applied to the photovoltaic system were compared and analyzed in terms of efficiency and power density according to the input voltage and load conditions. For accurate analysis of efficiency, the losses in each device of the single-phase and three-level boost converters were derived using mathematical equations and simulations by using the PSIM thermal module. Then, the losses were compared with the efficiency confirmed through the actual experiments. Results confirmed that the efficiency and power density can be improved by applying the three-level boost converter to the system according to the selection of the switching frequency.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.101-104
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• 2002

This paper propose that is algorithm of power dissipation reduction in the high level synthesis design for DSP(Digital Signal Processor), as the portable terminal system recently demand high power dissipation. This paper obtain effect of power dissipation reduction and switching activity that increase correlation of operands as input data of function unit. The algorithm search loop or repeatedly data to the input operands of function unit. That can be reduce the power dissipation using the new low power high level synthesis algorithm. In this Paper, scheduling operation search same nodes from input DFG(Data Flow Graph) with correlation coefficient of first input node and among nodes. Function units consist a multiplier, an adder and a register. The power estimation method is added switching activity for each bits of nodes. The power estimation have good efficient using proposed algorithm. This paper result obtain more Power reduction of fifty percents after using a new low power algorithm in a function unit as multiplier.

• Journal of electromagnetic engineering and science
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• v.15 no.3
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• pp.181-184
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• 2015

Evaluation of radiating radiofrequency fields from hand-held and body-mounted wireless communication devices to human bodies are conducted by measuring the specific absorption rate (SAR). The uncertainty of system validation and probe calibration in SAR measurement depend on the variation of RF power used for the validation and calibration. RF input power for system validation or probe calibration is controlled manually during the test process of the existing systems in the laboratories. Consequently, a long time is required to reach the stable power needed for testing that will cause less uncertainty. The standard uncertainty due to this power drift is typically 2.89%, which can be obtained by applying IEC 62209 in a normal operating condition. The principle of the Automatic Input Power Level Control System (AIPLC), which controls the equipment by a program that maintains a stable input power level, is suggested in this paper. The power drift is reduced to less than ${\pm}1.16dB$ by AIPLC, which reduces the standard uncertainty of power drift to 0.67%.

• Nuclear Engineering and Technology
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• v.49 no.2
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• pp.426-433
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• 2017

This paper describes the development process, the innovative techniques used and insights gained from the latest integrated, full scope, multistate Level 2 PSA analysis conducted at the Leibstadt Nuclear Power Plant (KKL), Switzerland. KKL is a modern single-unit General Electric Boiling Water Reactor (BWR/6) with Mark III Containment, and a power output of $3600MW_{th}/1200MW_e$, the highest among the five operating reactors in Switzerland. A Level 2 Probabilistic Safety Assessment (PSA) analyses accident phenomena in nuclear power plants, identifies ways in which radioactive releases from plants can occur and estimates release pathways, magnitude and frequency. This paper attempts to give an overview of the advanced modeling techniques that have been developed and implemented for the recent KKL Level 2 PSA update, with the aim of systematizing the analysis and modeling processes, as well as complying with the relatively prescriptive Swiss requirements for PSA. The analysis provides significant insights into the absolute and relative importances of risk contributors and accident prevention and mitigation measures. Thanks to several newly developed techniques and an integrated approach, the KKL Level 2 PSA report exhibits a high degree of reviewability and maintainability, and transparently highlights the most important risk contributors to Large Early Release Frequency (LERF) with respect to initiating events, components, operator actions or seismic component failure probabilities (fragilities).