• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.1371-1374
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• 1997

We had developed the on-line environmental monitoring system which has installed around Kori Nuclear Power Plants and will be taken the place of the existing system. The system consists of a main computer and 11 sets of radiation monitoring post equipments. Nal(Tl) scintillation detectro was adopted in addition to ion-chamber detector and implemented with DCU(Dose Conversion Unit) and SCA(Single Channel Analyzer). Compared with the existing system, it has revised feature in the radiation measurements which are detection of artificial radioactivity and 2-ways of the radiatiion detectors. The field test trsults show that the developed radiation detecting equipments can measure environmental radiation withn 5.0% of the theoretical value.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.86-89
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• 1999

In this paper, we propose a new architecture of the fast symbol timing synchronization system which has some shared hardware blocks in order to reduce the hardware complexity. The proposed system consists of received power detector, correlation power detector using shared complex moving adders, and 2-step peak detector. Our system has detected FFT starting point within three Symbols using first two reference symbols of the frame in wireless ATM system. The new architecture was designed and simulated using VHDL. Our proposed architecture also detects a correct symbol timing synchronization within three symbols under a multi-path fading channel.

• Fire Protection Technology
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• s.16
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• pp.13-19
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• 1994

An Experimental study on the relation between responsiveness and elapse of years This experiment study is to appraise a fire detector's durability & reliability. Fire detector is located in office, temp range 10-27 고 65 15%, installed in the ceiling with power on. This is the experiment report of elapsed 5 years.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.1
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• pp.52-56
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• 2014

In this paper, a high-efficiency power amplifier is implemented using a gate and drain bias control circuit for WPT (Wireless Power Transmission). This control circuit has been employed to improve the PAE (Power Added Efficiency). The gate and drain bias control circuits consists of a directional coupler, power detector, and operation amplifier. A high gain two-stage amplifier using a drive amplifier is used for the low input stage of the power amplifier. The proposed power amplifier that uses a gate and drain bias control circuit can have high efficiency at a low and high power level. The PAE has been improved up to 80.5%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.3
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• pp.503-510
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• 2006

Readout circuit is to convert signal occurred in a defector into suitable signal for image signal processing. In general, it has to possess functions of impedance matching with perception element, amplification, noise reduction and cell selection. It also should satisfies conditions of low-power, low-noise, linearity, uniformity, dynamic range, excellent frequency-response characteristic, and so on. The technical issues in developing image processing equipment for focal plane way (FPA) can be categorized as follow: First, ultraviolet (UV) my detector material and fine processing technology. Second, ReadOut IC (ROIC) design technology to process electric signal from detector. Last, package technology for hybrid bonding between detector and ROIC. ROIC enables intelligence and multi-function of image equipment. It is a core component for high value added commercialization ultimately. Especially, in development of high-resolution image equipment ROIC, it is necessary that high-integrated and low-power circuit design technology satisfied with design specifications such as detector characteristic, signal dynamic range, readout rate, noise characteristic, ceil pitch, power consumption and so on. In this paper, we implemented a $8\times8$ FPA prototype ROIC for reduction of period and cost. We tested unit block and overall functions of designed $8\times8$ FPA ROIC. Also, we manufactured ROIC control and image boards, and then were able to verify operation of ROIC by confirming detected image from PC's monitor through UART(Universal Asynchronous Receiver Transmitter) communication.

• Proceedings of the Korean Nuclear Society Conference
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• 2004.05a
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• pp.60.2-60.2
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• 2004

• Proceedings of the Korean Nuclear Society Conference
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• 2005.05a
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• pp.115-116
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• 2005

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.9
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• pp.1343-1347
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• 2013

This paper presents an analysis methods for current collection quality in catenary system by means of video image based monitoring system. Arcing is the sparking at the interface point between pantograph and contact wire when the electric trains have traction current values at speed. Percentage of arcing at maximum line speed is measurable parameters for compliance with the requirements on dynamic behaviour of the interface between pantograph and contact wire in accordance with requirement of IEC and EN standards. The arc detector and video is installed on a train aim at the trailing contact strip according to the travel direction. The arc detector presented and measured verity of value such as the duration and power density of each arc and the video image is measured a image when the arc is occurred in pantograph. In this paper we analysis of video image in accordance with power density of arcing from arc detector and compared with video image and power density of arcing so as to produce quality of arcing from image.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.35-38
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• 2018

This paper describes a low-power MPPT interface for DC-type energy harvesting sources. The proposed circuit consists of an MPPT controller, a bias generator, and a voltage detector. The MPPT controller consists of an MPG (MPPT Pulse Generator) with a schmitt trigger, a logic gate operating according to energy type (light, heat), and a sample/hold circuit. The bias generator is designed by employing a beta multiplier structure, and the voltage detector is implemented using a bulk-driven comparator and a two-stage buffer. The proposed circuit is designed with $0.35{\mu}m$ CMOS process. The simulation results show that the designed circuit consumes less than 100nA of current at an input voltage of less than 3V and the maximum power efficiency is 99.7%. The chip area of the designed circuit is $1151{\mu}m{\times}940{\mu}m$.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.1
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• pp.97-103
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• 2014

In this paper, a clock-data recovery using a 1/8-rate phase detector is proposed. The use of a conventional full or half-rate phase detector requires relatively higher frequency of a recovered clock, which is a burden on the design of a sampling circuit and a VCO. In this paper, a 1/8-rate phase detector is used to lower the frequency of the recovered clock and a linear equalizer is used as a input circuit of a phase detector to reduce the jitter of the recovered clock. A test chip fabricated in a 0.13-${\mu}m$ CMOS process is measured at 1.5-GHz for a 3-Gb/s PRBS input and 1.2-V power supply.