• Proceedings of the KIEE Conference
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• 1989.07a
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• pp.48-53
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• 1989

We attempt to achieve both high dynamic performance and maximal power efficiency by means of linear decoupling of rotor speed (or motor torque) and rotor flux. The induction motor with our controller possesses the input-output dynamic characteristics of a linear system such that the rotor speed (or motor torque) and the rotor flux are decoupled. The rotor speed (or motor torque) responses are not affected by abrupt changes in the rotor flux and vice versa. The rotor flux need not be measured but is estimated by the well-known flux simulator. The effect of large variation in the rotor resistance on the control performances is minimized by employing a parameter adaptation method. To illuminate the significance of our work. we present simulation and experimental results as well as mathematical performance analyses.

• Journal of Power Electronics
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• v.1 no.2
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• pp.88-98
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• 2001

An improved stationary frame-based digital current control technique for a permanent magnet(PM) synchronous motor is presented. Generally, the stationary frame current controller is known to provide the advantage of a simple implementation. However, there are some unavoidable limitations such as a steady-state error and a phase delay in the steady-state. On the other hand, in the synchronous frame current regulator the regulated currents are dc quantities and a zero steady-state error can be obtained through the integral control. However, the need to transform the signals between the stationary and synchronous frames makes the implementation of a synchronous frame regulator complex. Although the PI controller in the stationary frame gives a steady-state error and a phase delay, the control performance can be greatly improved by employing the exact decoupling control inputs for the back EMF., resulting in an ideal steady-state control characteristics irrespective of an operating condition as in the synchronous PI decoupling controller. However, its steady-state response may be degraded due to the inexact cancellation inputs under the parameter variations. To improve the control performance in the stationary frame, the disturbance is estimated using the time delay control. The proposed scheme is implemented on a PM synchronous motor using DSP TMS320C31 and the effectiveness is verified through the comparative simulations and experiments.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.2
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• pp.142-145
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• 2018

In this paper, we present a design technique for the suppression of common-mode(CM) noise in switched-mode power supply boards using the segmentation method. By applying the segmentation method, the example structure is decomposed into two segments with decoupling capacitors and a recombination matrix is extracted for the segments. The effects of the decoupling capacitor on CM noise suppression are examined. The simulation time is significantly reduced on using the segmentation method.

• Proceedings of the KIPE Conference
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• 2008.10a
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• pp.124-126
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• 2008

Grid Connected inverter is produced current to deliver power to grid. To provide low THD current, LCL filters is effective to filter high frequency component of current output from inverter. To provide sinusoidal waveform, there are many researchers have been proposed several controllers for grid-connected inverter controllers. Synchronous Reference Frame (SRF)-based controller is the most popular methods. SRF-based controller is capable for reducing both of zero-steady state error and phase delay. But SRF based controller is contained cross-coupling components, which generate some difficulties to analyze. In this paper, SRF based controller is analyzed. By applying decoupling control, cross-coupling component is eliminated and single phase model of the system is obtained. Through this single phase model, gain controller is designed. To reduce steady state error, proportional gain is set as high as possible, but it may produce instability. To compromise between a minimum steady state error and stability, the single phase model is evaluate through Root Locus and Bode diagram. PSIM simulation is used to verify the analysis.

• Journal of Power Electronics
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• v.19 no.5
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• pp.1289-1302
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• 2019

In this paper, an optimal allocation method of a hybrid active power filter in an active distribution network is designed based on the differential evolution algorithm to resolve the harmonic generation problem when a distributed generation system is connected to the grid. A distributed generation system model in the calculation of power flow is established. An improved back/forward sweep algorithm and a decoupling algorithm are proposed for fundamental power flow and harmonic power flow. On this basis, a multi-objective optimization allocation model of the location and capacity of a hybrid filter in an active distribution network is built, and an optimal allocation scheme of the hybrid active power filter based on the differential evolution algorithm is proposed. To verify the effect of the harmonic suppression of the designed scheme, simulation analysis in an IEEE-33 nodes model and an experimental analysis on a test platform of a microgrid are adopted.

• 한국신재생에너지학회:학술대회논문집
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• 2006.06a
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• pp.253-256
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• 2006

This paper shows operating characteristics of DFIG(Double Fed Induction Generator) for wind turbine. The back to back PWM voltage-fed inverter connected between the rotor and grid network operated sub and super-synchronous operating mode, and the vector-controlled DFIG enables the decoupling between active and reactive power as well as between torque and power factor. This paper is validated by simulations and experimental results.

• Proceedings of the KIPE Conference
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• 2020.08a
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• pp.357-358
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• 2020

본 논문에서는 커패시터-분할타입 능동전력디커플링 회로를 위한 가상 d-q전류 제어기 설계방법을 제안한다. 설계한 제어기의 주파수 특성을 분석하고 MATLAB/Simulink 시뮬레이션을 통해 검증한다.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.41-45
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• 2013

Modern electronic devices such as tablets and smartphones are getting more powerful and efficient. The demand in feature sets, functionality and usability increase exponentially and this has posed a great challenge to the design of a power distribution network (PDN). Power rails merging is a popular option used today in a PDN design as numerous power rails are no longer feasible due to form factor limitation and cost constraint. In this paper, the criteria and limitations for power rails merging are discussed. Despite having all the advantages such as pin count reduction, decoupling capacitors sharing, lower impedance and cost saving, power rails merging can however, introduce coupling noise to the system. In view of this, a PDN design with power rails merging that fulfills design recommendations and specifications such as noise target, power well placement, voltage supply values as well as power supply quadrant assignment is extremely important.

• Journal of Power Electronics
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• v.18 no.3
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• pp.817-825
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• 2018

In this paper, a current hysteresis control with good decoupling properties for doubly-fed brushless induction machines (BDFIMs) has been proposed based on a generalized vector model. The independent control of the reactive power and speed for BDFIMs has been achieved by controlling the d-axis and the q-axis current of the control windings (CW). The proposed vector control method has been developed for the power winding (PW) flux frame. Experimental verification of a type Y180M-4 BDFIM prototype with 1/4 pole-pairs has been presented. Evidence of its good performance has been shown through experimental results.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.143-146
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• 2011

A 50-MS/s 10-bit pipelined ADC with 1.2Vpp differential input range is proposed in this paper. The designed pipelined ADC consists of eight stage of 1.5bit/stage, one stage of 2bit/stage, digital error correction block, bias & reference driver, and clock generator. 1.5bit/stage is consists of sub-ADC, DAC and gain stage, Specially, a sample-and hold amplifier (SHA) is removed in the designed pipelined ADC to reduce the hardware and power consumption. Also, the proposed bootstrapped switch improves the Linearity of the input analog switch and the dynamic performance of the total ADC. The reference voltage was driven by using the on-chip reference driver without external reference. The proposed pipelined ADC was designed by using a 0.18um 1-poly 5-metal CMOS process with 1.8V supply. The total area including the power decoupling capacitor and power consumption are $0.95mm^2$ and 60mW, respectively. Also, the simulation result shows the ENOB of 9.3-bit at the Nyquist sampling rate.