• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.179-182
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• 2000

Adiabatic dynamic CMOS logic circuits, which are called ADCL circuits, promise us to implement low power logic circuits. Since the power supply source for ADCL circuits had not been developed, we proposed a power supply circuit for them. It is shown experimentally that by using the power supply circuit ADCL circuits can work with lower power consumption than conventional static CMOS circuit. In this paper, the power supply circuit is improved so that the power consumption can be reduced. Also, it is shown by some experiments that by using the circuit, ADCL circuits can work with lower power consumption than before Improving.

• Journal of Korea Multimedia Society
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• v.15 no.12
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• pp.1456-1463
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• 2012

In this paper, we study the ON/OFF control policy of base stations in two-tier heterogeneous cellular networks to minimize the total power consumption of the system. Using heterogeneous cellular networks is a potential approach of providing higher throughput and coverage compared to conventional networks with only macrocell deployment, but in fact heterogeneous cellular networks often operates regardless of total power consumption, which is a very important issue of modern cellular networks. We propose a policy that controls the activation/deactivation of base stations in heterogeneous cellular networks to minimize total power consumption. Under this policy, the total power consumed can be significantly reduced when the traffic is low while the QoS requirement is satisfied.

• Proceedings of the Korean Information Science Society Conference
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• 2002.04a
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• pp.676-678
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• 2002

In this work, we present the novel scheduling algorithm of the multimedia data retrieval for the mobile disk drive. Our algorithm is focused on minimizing the power consumption involved in data retrieval from the local disk drive. The prime commodity in mobile devices is the electricity. Strict restriction on power consumption requirement of the mobile device put unique demand in designing of its hardware and software components. State of the art disk based storage subsystem becomes small enough to be embedded in handhold devices. It delivers abundant storage capacity and portability. However, it is never be trivial to integrate small hard disk or optical disk drive in handhold devices due to its excessive power consumption. Our algorithm ARM in this article generates the optimal schedule of retrieving data blocks from the mobile disk drive while guaranteeing continuous playback of multimedia data.

• Journal of Korea Society of Digital Industry and Information Management
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• v.8 no.1
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• pp.41-46
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• 2012

In this paper, An efficient circuit design algorithm considering constraint is proposed. The proposed algorithm sets up in time constraint and area constraint, power consumption constraint for a circuit implementation. First, scheduling process for time constraint. Select the FU(Function Unit) which is satisfied with time constraint among the high level synthesis results. Analyze area and power consumption of selected FUs. Constraint set for area and power constraint. Device selection to see to setting condition. Optimization circuit implementation in selected device. The proposed algorithm compared with [7] and [8] algorithm. Therefore the proposed algorithm is proved an efficient algorithm for optimization circuit implementation.

• Journal of Environmental Impact Assessment
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• v.20 no.4
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• pp.465-475
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• 2011

It is known that energy consumption in bottom floor of typical Korean-style apartment is the highest. Previous studies for energy consumption in accordance with floor level appear to be very limited due to the dependence on single energy variable such as electric power or LNG separately, based on past flat type of apartment. Acknowledging these constraints, an empirical study for a tower type emerged recently as new style of apartment in South Korea was conducted to demonstrate how a comprehensive evaluation for both electric power and LNG consumption can be used to assist in monitoring the total energy consumption in terms of floor specific settings. It was possible to identify that energy consumption in bottom floor is lesser than that of top floor, to the contrary, fact known from previous study. Also electric power consumption in top floor was identified as 15% higher than that of floor in the least. It is anticipated that this integrated utilization of electric power and LNG data would present more scientific and objective evidence for the energy load among floor level of tower type apartment by overcoming serious constraints suffered from the past single variable investigation. Ultimately, the result in this paper could be used as a valuable reference to providing priority for energy saving activities in top floor such as cool roof or green roof.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.6 s.360
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• pp.1-8
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• 2007

In wireless sensor network which uses limited battery, power consumption is very important factor for the survivality of the system. By using low-power communication to reduce power consumption, error rate is increased in typical conditions. This paper analyzes power consumption of specific error control coding (ECC) implementations. With identical link quality, ECC provides coding gain which save the power for transmission at the cost of computing power. In sensor node, transmit power is higher than computing power of Micro Controller Unit (MCU). In this paper, Viterbi algerian is applied to the low-transmit-power sensor networks in terms of network power consumption. Practically, Viterbi algorithm presents 20% of reduction of re-transmission in compared with Auto Repeat Request (ARQ) system. Furthermore, it is observed that network power consumption is decreased by almost 18%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.37-43
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• 2008

This paper introduces a high-speed low-power self-timed current-mode logic (STCML) that reduces both dynamic and leakage power dissipation. STCML significantly reduces the leakage portion of the power consumption using a pulse-mode control for shorting the virtual ground node. The proposed logic style also minimizes the dynamic portion of the power consumption due to short-circuit current by employing an enhanced self-timing buffer. Comparison results using a 80-nm CMOS technology show that STCML achieves 26 times reduction on leakage power consumption and 27% reduction on dynamic power consumption as compared to the conventional current-mode logic. They also indicate that up to 59% reduction on leakage power consumption compared to differential cascode voltage switch logic (DCVS).

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.88-98
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• 2012

In this paper, the relationship between the bandwidth (BW) and power efficiency of a source follower based (SFB) filter is quantitatively analyzed, and a design methodology for a SFB filter for optimized BW - power consumption is introduced. The proposed design methodology achieves a maximum BW at a target quality (Q) factor for the given power consumption constraint by controlling design factors individually. In order to achieve the target BW from the maximized BW, a tuning method is introduced. Through the proposed design methodology, a fourth order Butterworth filter was implemented in 0.18 ${\mu}m$ CMOS technology. The measured BW, power consumption, and IIP3 are 100 MHz, 33 ${\mu}W$, and 9 dBm, respectively. Compared with other filter structures, the measured results show high BW - power efficiency.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.851-854
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• 2003

The low power motion estimation for MPEG-4 is a soft-core for hardwired motion estimation block in MPEG-4. This motion estimation is modified by 10 difference mode. So, this motion estimation decrease a power consumption compare conventional step search. This modified 4SS Low power Motion Estimation has been tested and verified to be valid for implementation of FPGA. The average PSNR between the original image and the motion-compensated image is 28.25dB. And Power consumption is 26mW.

• Journal of information and communication convergence engineering
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• v.5 no.2
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• pp.131-135
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• 2007

In this paper, The proposed algorithm consists of three steps. In the first step, TD(Transition Density) calculation has to be performed. a CLB-based CPLD low-power technology mapping algorithm considered a Trade-off is proposed. To perform low-power technology mapping for CPLDs, a given Boolean network has to be represented in a DAG. Total power consumption is obtained by calculating the switching activity of each node in a DAG. In the second step, the feasible clusters are generated by considering the following conditions: the number of inputs and outputs, the number of OR terms for CLB within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low-power technology mapping based on the CLBs packs the feasible clusters. The proposed algorithm is examined using SIS benchmarks. When the number of OR terms is five, the experiment results show that power consumption is reduced by 30.73% compared with TEMPLA, and by 17.11 % compared with PLA mapping.