• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.4
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• pp.277-284
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• 2017

For passive power factor correction, the valley fill circuit approach is attractive for low power applications because of low cost, high efficiency, and simple circuit design. However, to vouch for the product quality, two dc-link capacitors in the valley fill circuit should be selected to withstand the peak rectified ac input voltage. The common mode (CM) and differential mode (DM) choke should be used to suppress the electromagnetic interference (EMI) noise, thereby resulting in large size volume product. This paper presents the practical design and implementation of a valley fill flyback converter with reduced dc link capacitors and EMI magnetic volumes. By using the proposed over voltage protection circuit, dc-link capacitors in the valley fill circuit can be selected to withstand half the peak rectified ac input voltage, and the proposed CM/DM choke can be successfully adopted. The proposed circuit effectiveness is shown by simulation and experimentally verified by a 78W prototype.

• Journal of Power Electronics
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• v.15 no.2
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• pp.389-398
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• 2015

This paper presents a 1.92 kW resonant converter for medium voltage applications that uses low voltage stress MOSFETs (500V) to achieve zero voltage switching (ZVS) turn-on. In the proposed converter, four MOSFETs are connected in series to limit the voltage stress of the power switches at half of the input voltage. In addition, three resonant circuits are adopted to share the load current and to reduce the current stress of the passive components. Furthermore, the transformer primary and secondary windings are connected in series to balance the output diode currents for medium power applications. Split capacitors are adopted in each resonant circuit to reduce the current stress of the resonant capacitors. Two balance capacitors are also used to automatically balance the input capacitor voltage in every switching cycle. Based on the circuit characteristics of the resonant converter, the MOSFETs are turned on under ZVS. If the switching frequency is less than the series resonant frequency, the rectifier diodes can be turned off under zero current switching (ZCS). Experimental results from a prototype with a 750-800 V input and a 48V/40A output are provided to verify the theoretical analysis and the effectiveness of the proposed converter.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.3
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• pp.544-551
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• 2011

This paper presents the circuit arrangement and effective control method of regenerative energy storage system for an electric vehicle using super-capacitors as the braking energy storage element. A bi-directional controlled current flow of the DC-DC converters with the capacitor bank is connected in parallel with battery, and is controlled so that the whole of the braking energy is effectively absorbed into the capacitors and released back to the electric motor upon acceleration. The converter needs the series-parallel switching circuit for making the best use of the series capacitors and for limiting the step-up ratio of the boost converter. The proposed methods are verified by computer simulation and experimental set-up. They are usefully applied to the electric vehicles such as green cars, electric motorcycles, bike, etc which are power- supplied by the electric batteries.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.12
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• pp.20-27
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• 1997

In this paper, a multiplying digital-to-analog converter (MDAC) circuit for low-power high-resolution CMOS algorithmic A/D converters (ADC's) is proposed. The proposed MDAC is designed to operte properly at a supply at a supply voltge between 3 V and 5 V and employs an analog0domain power reduction technique based on a bias switching circuit so that the total power consumption can be optimized. As metal-to-metal capacitors are implemented as frequency compensation capacitors, opamps' performance can be varied by imperfect process control. The MDAC minimizes the effects by the circuit performance variations with on-chip tuning circuits. The proposed low-power MDAC is implementd as a sub-block of a 10-bit 200kHz algorithmic ADC using a 0.6 um single-poly double-metal n-well CMOS technology. With the power-reduction technique enabled, the power consumption of the experimental ADC is reduced from 11mW to 7mW at a 3.3V supply voltage and the power reduction ratio of 36% is achieved.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.3
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• pp.1-6
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• 2017

As the performance and density of IC devices increase, especially the clock frequency increases, power grid network integrity problems become more challenging. To resolve these power integrity problems, the use of passive devices such as resistor, inductor, and capacitor is very important. To manage the power integrity with little noise or ripple, decoupling capacitors are essential in electronic packaging. The decoupling capacitors are classified into voltage regulator capacitor, board capacitor, package capacitor, and on-chip capacitor. For next generation packaging technologies such as 3D packaging or wafer level packaging on-chip MIM decoupling capacitor is the key element for power distribution and delivery management. This paper reviews the use and necessity of on-chip decoupling capacitor.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.489-492
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• 2000

A novel low-cost simple and unity-power-factor electronic ballast is presented. The proposed electronic ballast employs a bypassing capacitor and load networks composed of ballast capacitors and small charge pump capacitors as power factor correction circuit combined with the secondary winding of the transformer in the self-excited current-fed push-pull resonant inverter(CF-PPRI) resulting in cost-effectiveness and higher efficiency. By analyzing the principles of power factor correction mathematically optimum design guidelines are presented. Since the lamps are used in power factor correction stage the input power is automatically adjusted according to the number of the lamps.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.66 no.4
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• pp.213-218
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• 2017

The DC electrolytic capacitor for DC-link of power converter is widely used in various power electronic circuits and system application. Its functions include, DC Bus voltage stabilization, conduction of ripple current due to switching events, voltage smoothing, etc. Unfortunately, DC electrolytic capacitors are some of the weakest components in power electronics converters. Many papers have proposed different algorithms or diagnosis method to determinate the ESR and tan ${\delta}$ capacitance C for fault alarm system of the electrolytic capacitor. However, both ESR vary with frequency and temperature. Accurate knowledge of both parameters at the capacitors operating conditions is essential to achieve the best reference data of fault alarm. According to parameter analysis, the capacitance increases with temperature and the initial ESR decreases. Higher frequencies make the reference ESR with the initial ESRo value to decrease. Analysis results show that the proposed DC Bus electrolytic capacitor reference ESR model setting technique can be applied to advanced reference signal of capacitor diagnosis systems successfully.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.266-269
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• 1999

Several power factor correction(PFC) circuits are presented to achieve high PF electronic ballast for both voltage-fed and current-fed electronic ballast. The proposed PFC circuits use valley-fill(VF) type DC-link stages modified from the conventional VF circuit to adopt the charge pumping method for PFC operations during the valley intervals. In voltage-fed ballast, charge pump capacitors are connected with the resonant capacitors. In current-fed type, the charge pump capacitors are connected with the additional secondary-side of the power transformer. The measured PF and THD are higher than 0.99 and 15% for all proposed PFC circuits. The lamp current CF is also acceptable in the proposed circuits. The proposed circuit is suitable for implementing cost-effective electronic ballast.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.61 no.1
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• pp.41-46
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• 2012

Electrolytic power capacitors have been widely used in power conversion system such as inverter or UPS because of characteristics of large capacitance, high-voltage and low-cost. The electrolytic capacitor, which is most of the time affected by the aging effect, plays a very important role for the power-electronics system quality and reliability. Therefore it is important to diagnosis monitoring the condition of an electrolytic capacitor in real-time to predict the failure. In this paper, the on-line remote diagnosis monitoring system for UPS DC link electrolytic capacitors using low-cost single-chip zigbee communication modules is developed. To estimate the health status of the capacitor, the equivalent series resistor(ESR) of the component has to be determined. The capacitor ESR is estimated by using RMS computation using BPF modeling of DC link ripple voltage/current. Zigbee-based hardware experimental results show that the proposed remote capacitor diagnosis monitoring system can be applied to UPS successfully.

• Journal of Power Electronics
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• v.11 no.3
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• pp.264-270
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• 2011

In this paper a novel passive snubber is proposed, which can suppress the voltage spike across the bridge leg of the isolated full-bridge boost topology. The snubber is composed of capacitors, inductors and diodes. Two capacitors connected in series are used to absorb the voltage spike and the energy of each capacitor can be transferred to the load during one switching cycle by the resonance of the inductors and capacitors. The operational principle of the passive snubber is analyzed in detail based on a three-phase power factor correction (PFC) converter, and the design considerations of both the converter and the snubber are given. Finally, a 3kW laboratory-made prototype is built. The experimental results verify the theoretical analysis and evaluations. They also prove the validity and feasibility of the proposed methods.