• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.21 no.8
• /
• pp.857-864
• /
• 2010

In this paper, we analyse the effect of the path imbalances(gain and phase mismatches) in LINC(LInear amplification with Nonlinear Component) system, and propose a simple scheme using LUTs(Look Up Table) to compensate the path imbalances. The EVM(Error Vector Magnitude) and ACPR(Adjacent Channel Power Ratio) of the LINC system are degraded significantly by the path imbalances because it adopts an outphasing technique. The EVM and ACPR are theoretically extracted for two variables(gain and phase mismatch factors) and 2-D LUTs for those are generated based on the analysis. The efficient and simple compensation scheme for the path imbalances is proposed using the 2-D LUTs. A LINC system with the suggested compensation scheme is implemented, and the proposed method is verified with an experiment. A 16-QAM signal with 1.5 MHz bandwidth is used. Before the compensation, the path gain ratio was 95 % and phase error was $19.33^{\circ}$. The proposed scheme adjusts those values with 99 % and $0.5^{\circ}$, and improves ACPR about 18.1 dB.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.16 no.11 s.102
• /
• pp.1059-1066
• /
• 2005

This paper reports an application of Doherty amplifier for efficiency improvement of feedforward power amplifier(FPA). For performance analysis, we measured 15 W average output power using WCDMA 4FA input signal with a center frequency 2.14 GHz. The applied Doherty amplifier presents the characteristics of high efficiency and low linearity in comparison to the class AB amplifier, and it was used as main amplifier of FPA fir efficiency improvement. To analyze the change of characteristic, tow Doherty amplifiers whose linearity and efficiency are different were applied. The applied FPAs are improved about $2\%$ or more performance in efficiency, but decreased in linearity on 15 W average output power. We additionally modified the coupling factor(CF) of the error loop and the error amplifier capacity for linearity improvement. Aa a result, the efficiency improvement and high linearity resulted from the change of CF and error amplifier capacity. However, we think if the linearity of Doherty amplifier were more than 35 dBc, the FPA would improve the performance about $2\%$ or more efficiency and maintain enough linearity.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.44 no.10
• /
• pp.185-190
• /
• 2007

In this paper, minimum sampling rates and method of nonlinear characterization were suggested for low power, quasi-memoryless PAs. So far, the Nyquist rate of the input signal has been used for nonlinear PA modeling, and it is burdening Analog-to-digital converters for wideband signals. This paper shows that the input Nyquist rate sampling is not a necessary condition for successful modeling of quasi-memoryless PAs. Since this sampling requirement relives the bandwidth requirements for Analog-to-digital converters (ADCs) for feedback paths in digital pre-distortion systems, relatively low-cost ADcs can be used to identify nonlinear PAs for wideband signal transmission, even at severe aliasing conditions. Simulation results show that a generic memoryless nonlinear RF power amplifier with AMAM and AMPM distortion can be successfully identified at any sampling rates. Measurement results show the modeling error variation is less than 0.8dB over any sampling rates.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.9
• /
• pp.31-39
• /
• 2011

In this paper, we propose a signal readout system with small area and low power consumption for CNT sensor arrays. The proposed system consists of signal readout circuitry, a digital controller, and UART I/O. The key components of the signal readout circuitry are 64 transimpedance amplifiers (TIA) and SAR-ADC with 11-bit resolution. The TIA adopts an active input current mirror (AICM) for voltage biasing and current amplification of a sensor. The proposed architecture can reduce area and power without sampling rate degradation because the 64 TIAs share a variable gain amplifier (VGA) which needs large area and high power due to resistive feedback. In addition, the SAR-ADC is designed for low power with modified algorithm where the operation of the lower bits can be skipped according to an input voltage level. The operation of ADC is controlled by a digital controller based on UART protocol. The data of ADC can be monitored on a computer terminal. The signal readout circuitry was designed with 0.13${\mu}m$ CMOS technology. It occupies the area of 0.173 $mm^2$ and consumes 77.06${\mu}W$ at the conversion rate of 640 samples/s. According to measurement, the linearity error is under 5.3% in the input sensing current range of 10nA - 10${\mu}A$. The UART I/O and the digital controller were designed with 0.18${\mu}m$ CMOS technology and their area is 0.251 $mm^2$.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.7
• /
• pp.17-26
• /
• 2016

This work proposes a 12b 60MS/s 0.18um CMOS Flash-SAR ADC for various systems such as wireless communications and portable video processing systems. The proposed Flash-SAR ADC alleviates the weakness of a conventional SAR ADC that the operation speed proportionally increases with a resolution by deciding upper 4bits first with a high-speed flash ADC before deciding lower 9bits with a low-power SAR ADC. The proposed ADC removes a sampling-time mismatch by using the C-R DAC in the SAR ADC as the combined sampling network instead of a T/H circuit which restricts a high speed operation. An interpolation technique implemented in the flash ADC halves the required number of pre-amplifiers, while a switched-bias power reduction scheme minimizes the power consumption of the flash ADC during the SAR operation. The TSPC based D-flip flop in the SAR logic for high-speed operation reduces the propagation delay by 55% and the required number of transistors by half compared to the conventional static D-flip flop. The prototype ADC in a 0.18um CMOS demonstrates a measured DNL and INL within 1.33LSB and 1.90LSB, with a maximum SNDR and SFDR of 58.27dB and 69.29dB at 60MS/s, respectively. The ADC occupies an active die area of $0.54mm^2$ and consumes 5.4mW at a 1.8V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.19 no.12
• /
• pp.1339-1349
• /
• 2008

In this paper, a nonlinear relationship between an input complex envelope and an output complex envelope of m-th harmonic zone is theoretically analyzed, and AM/$AM_m$ and AM/$PM_m$ are defined. A scheme to extract these characteristics from measured in-phase and quadrature-phase data is suggested. The proposed analysis is verified with a fundamental-fundamental and fundamental-third harmonic measurements for a InGaP power amplifier(PA). Based on the harmonic-band nonlinear analysis and extraction scheme, a new technique to send a signal in m-th harmonic band with a harmonic signal Linearization Digital Predistortion(DPD) scheme is presented. A numerical analysis and a Look-Up Table(LUT) based DPD algorithms to linearize output signal on m-th harmonic zone are developed. For a 16- and a 64-QAM input signals, a DPD for third harmonic signal linearization is implemented, and output spectrum and signal constellation are measured. The wholly distorted signals are linearized, and thus the measured Error Vector Magnitudes (EVM) are 6.4 % and 6.5 % respectively. The results show that a proposed scheme linearizes a nonlinearly distorted harmonic band signals. The proposed nonlinear analysis and predistortion scheme can be applied to multiband transmitter in next generation software defined radio(SDR)/cognitive radio(CR) wireless system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.23 no.1
• /
• pp.76-84
• /
• 2012

In this paper, two kinds of E-plane microstrip-to-waveguide transitions are optimally designed and fabricated for combining output power from multiple small-power amplifiers in a WR-28 waveguide because conventional K connectors cause unnecessary insertion loss and adaptor loss. The transition design is based on target specifications such as a center frequency of 35 GHz, bandwidth of ${\pm}500MHz$, 0.1 dB insertion loss and 20 dB return loss. Performance variation caused by mechanical tolerance and assembly deviation is fully evaluated by three dimensional electromagnetic simulation. The fabricated back-to-back transitions with 16 mm and 26.57 mm interstage microstrip lines show insertion loss per transition of ~0.1 dB at 35 GHz and average 0.2 dB over full Ka band. Also the back-to-back transition shows return loss greater than 15 dB, which implies that the transition itself has return loss better than 20 dB.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.21 no.4
• /
• pp.443-451
• /
• 2010

This paper describes a fully integrated CMOS low-IF mobile-TV RF tuner for Band-III T-DMB/DAB applications. All functional blocks such as low noise amplifier, mixers, variable gain amplifiers, channel filter, phase locked loop, voltage controlled oscillator and PLL loop filter are integrated. The gain of LNA can be controlled from -10 dB to +15 dB with 4-step resolutions. This provides a high signal-to-noise ratio and high linearity performance at a certain power level of RF input because LNA has a small gain variance. For further improving the linearity and noise performance we have proposed the RF VGA exploiting Schmoock's technique and the mixer with current bleeding, which injects directly the charges to the transconductance stage. The chip is fabricated in a 0.18 um mixed signal CMOS process. The measured gain range of the receiver is -25~+88 dB, the overall noise figure(NF) is 4.02~5.13 dB over the whole T-DMB band of 174~240 MHz, and the measured IIP3 is +2.3 dBm at low gain mode. The tuner rejects the image signal over maximum 63.4 dB. The power consumption is 54 mW at 1.8 V supply voltage. The chip area is $3.0{\times}2.5mm^2$.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.45 no.12
• /
• pp.42-48
• /
• 2008

Next generation wireless communication systems require RF transceivers that enable multiband/multimode operations. Polar transmitters are known as good candidates for high data rate systems such as EDGE (Enhanced Data Rates for GSM Evolution), WCDMA (Wideband Code Division Multiple Access), and WLAN (Wireless Local Area Network) because they can obtain high efficiency by using efficient switched-mode RF power amplifiers. In this paper, we investigate the performance of a simple peak windowing scheme for the OFDM (Orthogonal frequency Division Multiplexing) polar transmitter, which requires no change of a receiver structure or no additional information transmission. The approach we employed is to apply the peak windowing scheme to the amplitude modulated signals of the polar transmitter to reduce the PAPR (Peak-to-Average Power Ratio). The BER (Bit Error Rate) and EVM (Error Vector Magnitude) performances are measured for various window types and lengths. The simulation results demonstrate that the proposed algorithm mitigates out-of-band distortion introduced by clipping along with PAPR reduction.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.11
• /
• pp.828-835
• /
• 2001

Novel bipolar transresistance amplifier(TRA) and its offset-compensated TRA for high-performance current-mode signal processing are described. The TRA consist of two current follower for a current inputs, a current summer for the current-difference, a resistor for the current to voltage converter, and a voltage follower for the voltage output. The offset-compensated TRA adopts diode-connected npn and pnp transistor to reduce offset voltage in the TRA. The simulation results show that the TRA has impedance of 0.5 Ω at the input and the output terminal. The offset voltages at these terminals is 40 mV The offset-compensated TRA has the offset voltage of 1.1 mV and the impedance of 0.25 Ω. The 3-dB cutoff frequency is 40 MHz for the two TRA＇s when used as a current to voltage converter with unit-gain transresistance. The power dissipation is 11.25 mW.