• Title/Summary/Keyword: Post metal annealing.

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Effects of post-annealing and seeding layers on electrical properties of PLT thin films by MOCVD using ultrasonic spraying (후열처리 및 seeding 층이 초음파분무 MOCVD법에 의한 PLT 박막 제조 시 전기적 특성에 미치는 영향)

  • 이진홍;김기현;박병옥
    • Journal of the Korean Crystal Growth and Crystal Technology
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    • v.12 no.5
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    • pp.247-252
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    • 2002
  • $(Pb_{1-x}La_x)TiO_3$ (x = 0.1) thin films were prepared on ITO-coated glass substrates by metal organic chemical vapor deposition using ultrasonic spraying. Effects of the post-annealing and the seeding layer on crystallization, microstructures and electrical properties of thin films were investigated. Dielectric constants of films increased due to the modification of crystallization and the changing of a surface morphology by applying the post-annealing. In addition, as the application of PT seed- ing layer offered nucleation sites to PLT thin films, electrical properties of films were enhanced by the increase of crys-tallinity and grain size. The dielectric constant of the films post-heated for 60 min and with a seeding layer was 213 at 1 kHz.

Effect of High Pressure Deuterium post-annealing Annealing on the Electrical and Reliability properties of 80nm DRAM (80nm DRAM의 고압중수소 열처리에 따른 전기적 신뢰성 특성 영향)

  • Chang, Hyo-Sik;Cho, Kyoon;Suh, Jai-Bum;Hong, Sung-Joo;Jang, Man;Hwang, Hyun-Sang
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.11a
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    • pp.117-118
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    • 2008
  • High-pressure deuterium annealing process is proposed and investigated for enhanced electrical and reliability properties of 512Mb DDR2 DRAM without increase in process complexity. High pressure deuterium annealing (HPDA) introduced during post metal anneal (PMA) improves not only DRAM performance but also reliability characteristics of MOSFET. Compared with a control sample annealed in a conventional forming gas, additional annealing in a high pressure deuterium ambient at $400^{\circ}C$ for 30 min decreased G1DL current and junction leakage. The improvements can be explained by deuterium incorporation at $SiO_2$/Si substrate interface near isolation trench edge.

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The thermal annealing effect on electrical performances of a-Si:H TFT fabricated on a metal foil substrate

  • Han, Chang-Wook;Nam, Woo-Jin;Kim, Chang-Dong;Kim, Ki-Yong;Kang, In-Byeong;Chung, In-Jae;Han, Min-Koo
    • 한국정보디스플레이학회:학술대회논문집
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    • 2007.08a
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    • pp.745-748
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    • 2007
  • Hydrogenated amorphous silicon thin film transistors (a-Si:H TFTs) were fabricated on a flexible metal substrate at $150\;^{\circ}C$. To increase the stability of the flexible a-Si:H TFTs, they were thermally annealed at $230\;^{\circ}C$. The field effect mobility was reduced because of the strain in a- Si:H TFT under thermal annealing.

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Leakage Current Mechanism of Thin-Film Diode for Active-Matrix Liquid Crystal Displays

  • Lee, Myung-Jae;Chung, Kwan-Soo;Kim, Dong-Sik
    • Journal of Korean Vacuum Science & Technology
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    • v.6 no.3
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    • pp.126-132
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    • 2002
  • The origin of image-sticking in metal-insulator-metal type thin-film diode liquid crystal displays(TFD-LCDs) is the asymmetric current-voltage(I-V) characteristic of TFD element. We developed that TFD-LCDs have reduced-image-sticking. Tantalum pentoxide(Ta$_2$O$\sub$5/) is a candidate for use in metal-insulator-metal(MIM) capacitors in switching devices for active-matrix liquid crystal displays(AM-LCDs). High quality Ta$_2$O$\sub$5/ thin films have been obtained from anodizing method. We fabricated a TFD element using Ta$_2$O$\sub$5/ films which had perfect current-voltage symmetry characteristics. We applied novel process technologies which were postannealed whole TFD element instead of conventional annealing to the fabrication. One-Time Post-Annealing(OPTA) heat treatment process was introduced to reduce the asymmetry and shift of the I-V characteristics, respectively. OPTA means that the whole layers of lower metal, insulator, and upper metal are annealed at one time. Futhermore, in this paper, we discussed the effects of top-electrode metals and annealing conditions.

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Effect of post-annealing on single-walled carbon nanotubes synthesized by arc-discharge

  • Park, Suyoung;Choi, Sun-Woo;Jin, Changhyun
    • Journal of Ceramic Processing Research
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    • v.20 no.4
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    • pp.388-394
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    • 2019
  • In this study, high-purity single-walled carbon nanotubes (SWCNTs) were prepared by removing the unreacted metal constituents and amorphous carbon impurities using a post-annealing process. Unlike conventional thermal processing techniques, this technique involved different gas atmospheres for efficient removal of impurities. A heat treatment was conducted in the presence of chlorine, oxygen, and chlorine + oxygen gases. The nanotubes demonstrated the best characteristics, when the heat treatment was conducted in the presence of a mixture of chlorine and oxygen gases. The scanning electron microscopy, transmission electron microscopy, ultraviolet absorbance, and sheet resistance measurements showed that the heat treatment process efficiently removed the unreacted metal and amorphous carbon impurities from the as-synthesized SWCNTs. The high-purity SWCNTs exhibited improved electrical conductivities. Such high-purity SWCNTs can be used in various carbon composites for improving the sensitivity of gas sensors.

Effects of lead metal and annealing methods on low resistance contact formation of polycrystalline CdTe thin film (다결정 CdTe박막의 저저항 접축을 위한 배선금속 및 열처리방법의 효과에 관한 연구)

  • 김현수;이주훈;염근영
    • Electrical & Electronic Materials
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    • v.8 no.5
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    • pp.619-625
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    • 1995
  • Polycrystalline CdTe thin film has been studied for photovoltaic application due to the 1.45 eV band gap energy ideal for solar energy conversion and high absorption coefficient. The formation of low resistance contact to p-CdTe is difficult because of large work function(>5.5eV). Common methods for ohmic contact to p-CdTe are to form a p+ region under the contact by in-diffusion of contact material to reduce the barrier height and modify a p-CdTe surface layer using chemical treatment. In this study, the surface chemical treatment of p CdTe was carried out by H$\_$3/PO$\_$4/+HNO$\_$3/ or K$\_$2/Cr$\_$2/O$\_$7/+H$\_$2/SO$\_$4/ solution to provide a Te-rich surface. And various thin film contact materials such as Cu, Au, and Cu/Au were deposited by E-beam evaporation to form ohmic contact to p-CdTe. After the metallization, post annealing was performed by oven heat treatment at 150.deg. C or by RTA(Rapid Thermal Annealing) at 250-350.deg. C. Surface chemical treatments of p-CdTe thin film improved metal/p-CdTe interface properties and post heat treatment resulted in low contact resistivity to p-CdTe.Of the various contact metal, Cu/Au and Cu show low contact resistance after oven and RTA post-heat treatments, respectively.

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The Effect of the Heat Treatment of the ZrO2 Buffer Layer and SBT Thin Film on Interfacial Conditions and Ferroelectric Properties of the SrBi2Ta2O9/ZrO2/Si Structure (ZrO2 완충층과 SBT 박막의 열처리 과정이 SrBi2Ta2O9/ZrO2/Si 구조의 계면 상태 및 강유전 특성에 미치는 영향)

  • Oh, Young-Hun;Park, Chul-Ho;Son, Young-Guk
    • Journal of the Korean Ceramic Society
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    • v.42 no.9 s.280
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    • pp.624-630
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    • 2005
  • To investigate the possibility of the $ZrO_2$ buffer layer as the insulator for the Metal-Ferroelectric-Insulator-semiconductor (MFIS) structure, $ZrO_2$ and $SrBi_2Ta_2O_9$ (SBT) thin films were deposited on the P-type Si(111) wafer by the R.F. magnetron-sputtering method. According to the process with and without the post-annealing of the $ZrO_2$ buffer layer and SBT thin film, the diffusion amount of Sr, Bi, Ta elements show slight difference through the Glow Discharge Spectrometer (GDS) analysis. From X-ray Photoelectron Spectroscopy (XPS) results, we could confirm that the post-annealing process affects the chemical binding condition of the interface between the $ZrO_2$ thin film and the Si substrate. Compared to the MFIS structure without the post-annealing of the $ZrO_2$ buffer layer, memory window value of MFlS structure with post-annealing of the $ZrO_2$ buffer layer were considerably improved. The window memory of the Pt/SBT (260 nm, $800^{\circ}C)/ZrO_2$ (20 nm) structure increases from 0.75 to 2.2 V under the applied voltage of 9 V after post-annealing.

A Study on the LCD(Liquid Crystal Display) Device which have MIM (Meta1-lnsulator- Meta1) Structure (MIM(Metal-Insulator-Metal)구조의 LCD(Liquid Crystal Display)소자 특성 연구)

  • 최광남;이명재;곽성관;정관수;김동식
    • Proceedings of the IEEK Conference
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    • 2001.06b
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    • pp.209-212
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    • 2001
  • High quality Taros thin films have been obtained from anodizing. The as-deposited amorphous films have excellent physical and electrical properties: refractive indices ~2.15, dielectric constants ~25, and leakage currents <10$^{-8}$ Ac $m^{-2}$ at 1MV $cm^{-1}$ , 700$\AA$ thickness. We fabricated a MIM element with theses T $a_2$ $O_{5}$ films which had perfect current-voltage symmetry characteristics using a new process technology which was post annealing of whole MIM element instead of conventional annealing conditions (top-electrode metals, annealing conditions) on the capacitor performances were extensively discussed throughout this work.k.

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Fabrication of branched Ga2O3 nanowires by post annealing with Au seeds

  • Lee, Mi-Seon;Seo, Chang-Su;Gang, Hyeon-Cheol
    • Proceedings of the Korean Vacuum Society Conference
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    • 2015.08a
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    • pp.203-203
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    • 2015
  • Gallium Oxide (Ga2O3) has been widely investigated for the optoelectronic applications due to its wide bandgap and the optical transparency. Recently, with the development of fabrication techniques in nanometer scale semiconductor materials, there have been an increasing number of extensive reports on the synthesis and characterization of Ga2O3 nano-structures such as nano-wires, nano-belts, and nano-dots. In contrast to typical vapor-liquid-solid growth mode with metal catalysts to synthesis 1-dimensional nano-wires, there are several difficulties in fabricating the nano-structures by using sputtering techniques. This is attributed to the fact that relatively low growth temperatures and higher growth rate compared with chemical vapor deposition method. In this study, Ga2O3 nanowires (NWs) were synthesized by using radio-frequency magnetron sputtering method. The NWs were then coated by Au thin films and annealed under Ar or N2 gas enviroment with no supply of Gallium and Oxygen source. Several samples were prepared with varying the post annealing parameters such as gas environment annealing time, annealing temperature. Samples were characterized by using XRD, SEM, and PL measurements. In this presentation, the details of fabrication process and physical properties of branched Ga2O3 NWs will be reported.

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Study on Electrical Characteristics of Hafnium Silicate Films with Low Temperature O2 Annealing (저온 Osub2 어닐링 공정을 통한 HfSixOy의 전기적 특성 개선)

  • Lee, Jung-Chan;Kim, Kwang-Sook;Jeong, Seok-Won;Roh, Yong-Han
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.24 no.5
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    • pp.370-373
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    • 2011
  • We investigated the effects of low temperature ($500^{\circ}C$) $O_2$ annealing on the characteristics of hafnium silicate ($HfSi_xO_y$) films deposited on a Si substrate by atomic layer deposition (ALD). We found that the post deposition annealing under oxidizing ambient causes the oxidation of residual Hf metal components, resulting in the improvement of electrical characteristics such as flat band voltage shift (${\Delta}V_{fb}$) by hysteresis without oxide capacitance reduction. We suggest that post deposition annealing under oxidizing ambient is necessary to improve the electrical characteristics of $HfSi_xO_y$ films deposited by ALD.