• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.401-404
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• 2004

Transfer characteristics of poly-Si TFTs within process window of laser energy are investigated. In terms of surface morphology and transfer characteristics, process window of laser crystallization is evaluated. While maximum mobility exists in lower edge of process window in n-channel TFTs, maximum mobility exists in higher edge of process window in p-channel TFTs.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1028-1031
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• 2009

High quality poly-SiGe thin films were prepared on 6-inch substrates using Reactive-thermal CVD with $Si_2H_6$ and $GeF_4$ around at $500^{\circ}C$ directly. Its thickness uniformity was ~ 3% on the entire substrate area. N-channel mobility of ~30 nm thick bottom-gate TFTs exceeded 20 $cm^2$/Vs without any further crystallization.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.1791-1793
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• 2000

본 연구에서는 다결정 실리콘 박막 트랜지스터(poly-Si TFTs)에서의 소오스 및 드레인 영역 형성을 위해 PSG (phosphosilicate glass)와 BSG (borosilicate glass) 박막을 도핑 물질(dopant)로 하여 저온에서 엑시머 레이저(eximer laser)로 활성화하는 공정을 제안한다. 이 실험을 통해 소스 가스인 $PH_3$와 $SiH_4$의 유량비, 레이저 에너지 밀도와 레이저 조사 횟수를 변화시키면서 면저항(sheet resistance)과 불순물의 확산 깊이(diffusion depth)를 성공적으로 조절하였다. 불순물의 확산 깊이와 표면 농도는 레이저 에너지 밀도와 조사 횟수를 증가시킴에 따라 증가하였으며 그 결과 최소 면저항 값은 인(P)의 경우 450$\Omega/\square$을 얻었고 붕소(B)의 경우 1100$\Omega/\square$을 얻었다. 이러한 실험결과는 제안된 방법을 통해 poly-Si TFTs 에서 소오스, 드레인 영역의 도핑 공정을 수행할 수 있음을 보여준다.

• Journal of Information Display
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• v.4 no.3
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• pp.17-21
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• 2003

A low temperature doping technique to be applied in poly-Si TFTs on plastic substrates was investigated. Heavily-doped amorphous silicon layers were deposited on poly-Si and the dopant atoms were driven in by subsequent excimer laser annealing. The entire process was carried out under a substrate temperature of 120 $^{\circ}C$, and a sheet resistance of as low as 300 ${\Omega}$/sq. was obtained.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.12
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• pp.68-74
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• 1998

Improved performance and suppressed short-channel effects of polysilicon thin film transistors (poly-Si TFTs) with very thin electron cyclotron resonance (ECR) $N_2$O-plasma gate oxide have been investigated. Poly-Si TFTs with ECR $N_2$O-plasma oxide ($N_2$O-TFTs) show better performance as well as suppressed short-channel effects than those with conventional thermal oxide. The fabricated $N_2$O-TFTs do not show threshold voltage reduction until the gate length is reduced to 3 ${\mu}{\textrm}{m}$ for n-channel and 1 ${\mu}{\textrm}{m}$ for p-channel, respectively. The improvements are due to the smooth interface, passivation effects, and strong Si ≡ N bonds.

• Journal of Information Display
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• v.4 no.4
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• pp.1-3
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• 2003

For excimer laser annealing (ELA), energy density, number of pulses, beam uniformity, and condition of initial amorphous Si (a-Si) films are significant factors contributing to the final microstructure and the performance of low-temperature polycrystalline Si (LTPS) TFTs. Although the process and equipment have been significantly improved, the environmental factors associated with initial amorphous Si (a-Si) films and process conditions are yet to be optimized.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.93-94
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• 2007

다양한 LDD(lightly doped drain)에 따른 n-channel poly-Si TFT (thin film transistor)에 대하여 보고한다. 유리 기판 위에 ELA를 이용하여 만들어진 Polycrystalline silicon (poly-Si)은 TFT-LCD의 응용을 위한 재료로써 우수한 특성을 갖는다. 제작된 n-channel TFT는 절연층으로 $SiN_x$, $SiO_2$의 이중 구조를 갖는다. 다양한 LDD에 따른 n-channel poly-Si TFT의 문턱전압($V_{TH}$), ON/OFF 전류비 ($I_{ON}/I_{OFF}$), 포화전류($I_{DSAT}$)는 TFT의 보다 좋은 성능을 위해 연구된다. 짧은 LLD 길이를 가진 n-channel poly-Si TFT의 문턱전압은 작고, 포화전류의 값은 크다. 또한 긴 LLD 길이를 가진 n-channel poly-Si TFT는 작은 kink effect를 가진다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.40-40
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• 2009

The electrical characteristic of the conventional self-aligned polycrystalline silicon (poly-Si) TFTs are known to present several undesired effects such as large leakage current, kink effect and hot-carrier effects. In this paper, LTPS TFTs with different GOLDD length were fabricated and investigated the effect of the GOLDD. GOLDD length of 1, 1.5 and $2{\mu}m$ were used, while the thickness of the gate dielectrics($SiN_x/SiO_2$) was fixed at 65nm(40nm/25nm). The electrical characteristics show that the kink effect is reduced at the LTPS TFTs, and degradation from the hot-carrier effect was also decreased by increasing GOLDD length.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.261-264
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• 2007

We developed a non self-aligned poly-silicon TFTs fabrication process at two different temperatures on spin-coated polyimide layer above Si-wafer. After TFTs fabrication, the polyimide layer was mechanically released from the Si-wafer and the devices characteristics were compared. In addition self-heating and hot-carrier induced instabilities were analysed.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.747-750
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• 2005

In this paper, we propose a new level shifter circuit for reducing power consumption. The concept of the proposed level shifter is to use capacitive coupling effect to reduce short circuit current. The power consumption of the proposed level shifter is reduced up to 50%, compared to the conventional level shifter. Especially the proposed level shifter circuit works well with low temperature poly-Si (LTPS) TFTs. It can operate on low input voltage even with low-mobility, high and widely-varying threshold voltage of LTPS TFT.