• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.211-213
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• 1999

In this paper, we documented the controlling oxide removal amount on the pattern wafer using removal rate and removal thickness of blanket wafer. There was the strong correlation relationship for both(correlation factor:0.7109). So, we could confirm the repeatability as applying for STI CMP process from the obtained linear formular. As the result of repeatability test, the difference of calculated polishing time and actual polishing time was 3.48 seconds based on total 50 lots. If this time is converted into the thickness, it is from 104$\AA$ to 167$\AA$. It is possible to be ignored because it is under the process margin.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.12 no.2
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• pp.114-120
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• 2013

An EP(Electrolytic Polishing)-MAP(Magnetic Abrasive Polishing) hybrid process was applied to remove burr on the micro pattern. Micro pattern fabrication processes are combined with micro milling and EP-MAP hybrid process for deburring. Depending on the micro milling conditions which are applied, micro burrs are formed around the side and top of the pattern. The EP-MAP deburring is used to remove these burrs effectively. To optimize removal rate and form error in the EP-MAP hybrid process, a design of experiment was performed. The effect of deburring process and form error of micro pattern are evaluated via SEM images and the results of AFM.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.5
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• pp.420-425
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• 2008

PMMA light guiding plate with nano-sized pattern was fabricated using anodized aluminum oxide membrane as a template for nano imprint lithography. Nano-sized pore arrays were prepared by the self-organization processes of the anodic oxidation using the aluminum plate with 99.999% purity. Since the aluminum plate has a rough surface, the aluminum plate with thickness of 1mm was anodized after the pre-treatments of chemical polishing, and electrochemical polishing. The surface morphology of the alumina obtained by the first anodization process was controlled by the concentration of electrochemical solution during the first anodization. The surface morphology of the alumina was also changed according to temperature of the solution during chemical polishing performed after first anodization. The pore widening process was employed for obtaining the one-channel with flat surface and height of the channel because the pores of the alumina membrane prepared by the fixed voltage method shows the structure of two-channel with rough surface. It is shown from SPM results that the nano-sized pattern on PMMA light guiding plate fabricated by nano imprint lithography method was well transferred from that of anodized aluminum oxide template.

• Transactions on Electrical and Electronic Materials
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• v.7 no.4
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• pp.163-166
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• 2006

The dishing and the erosion were evaluated on the tungsten CMP process with conventional and new developed slurry. The tungsten thin film was polished by orbital polishing equipment. Commercial pattern wafer was used for the evaluation. Both slurries were pre tested on the oxide region on the wafer surface and the removal rate was not different very much. At the pattern density examination, the erosion performance was increased at all processing condition due to the reduction of thickness loss in new slurry. However, the dishing thickness was not remarkably changed at high pattern density despite of the improvement at low pattern density. At the large pad area, the reduction of dishing thickness was clearly found at new tungsten slurry.

• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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• 2002.10b
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• pp.435-437
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• 2002

Polishing of copper, a process called copper chemical mechanical polishing, is a critical, intermediate step in the planarization of silicon wafers. During polishing, the electrodeposited copper films are removed by slurries: and the differential polishing rates between copper and the surrounding silicon dioxide leads to a greater removal of the copper. The differential polishing develops dimples and furrows; and the process is called dishing and erosion. In this work, we present the results of experiments on dishing and erosion of copper-CMP, using patterned silicon wafers. Results are analyzed for the pattern factors and properties of the copper layers. Three types of pads - plain, perforated, and grooved - were used for polishing. The effect of slurry chemistries and pad soaking is also reported.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.10a
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• pp.935-938
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• 1997

Recently, the minimum line width shows a tendency to decrease and the multi-level increase in semiconductor. Therefore, a planarization technique is needed and chemical mechanical polishing(CMP) is considered as one of the most suitable process. CMP accomplishes a high polishing performance and a global planarization of high quality. But there are several defects in CMP such as micro-scratches, abrasive contaminations, and non-uniformity of polished wafer edges. Wet etching include of Spin-etching can improve he defects of CMP. It uses abrasive-free chemical solution instead of slurry. On this study, ILD(INterlayer-Dielectric) was removed by CMP and wet-etching methods in order to investigate the superiority of wet etching mechanism. In the thin film wafer, the results were evaluated at a viewpoint of material removal rate(MRR) and within wafer non-uniformity(WIWNU). And pattern step height was also compared for planarization characteristics of the patterned wafer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.113-114
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• 2005

Sufficient removal rate with adequate selectivity to realize the pattern mask of tetra-ethyl ortho-silicate (TEOS) film for the vertical sidewall angle were obtained by chemical mechanical polishing (CMP) with commercial silica slurry as a function of pH variation. The changes of X-ray diffraction pattern and dielectric constant by CMP process were negligible.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.10a
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• pp.39-40
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• 2012

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.19 no.5
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• pp.616-621
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• 2010

New type of the base material of the light-emitting diode requires copper wafer in view of heat and electrical conductance. Therefore, polishing process of the substrate level is needed to get a nanometer level of surface roughness as compared with pattern structure of nano-size in the semiconductor industry. In this paper, a series of lapping and polishing technique is shown for the rough and deflected copper substrate of thickness 3mm. Lapping by sand papers tried air cooling method. And two steps of polishing used the diamond abrasives and the $Al_2O_3$ slurry of size 100mm considering the residual scratch. White-light interferometer proved successfully a mirror-like surface roughness of Ra 6nm on the area of $0.56mm{\times}0.42mm$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.3
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• pp.203-207
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• 2008

Chemical mechanical polishing (CMP) allows the planarization of wafers with two or more materials. There are many elements such as slurry, polishing pad, process parameters and conditioning in CMP process. Especially, polishing pad is considered as one of the most important consumables because this affects its performances such as WIWNU(within wafer non-uniformity) and MRR(material removal rate). In polishing pad, grooves and pores on its surface affect distribution of slurry, flow and profile of MRR on wafer. A subject of this investigation is to apply CMP for planarization of shallow trench isolation structure using microstructure(MS) pad. MS pad is designed to have uniform structure on its surface and manufactured by micro-molding technology. And then STI CMP performances such as pattern selectivity, erosion and comer rounding are evaluated.