• Journal of the Korean institute of surface engineering
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• v.48 no.6
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• pp.360-370
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• 2015

As the size of the semiconductor devices shrinks to nanometer scale, the importance of plasma etching process to the fabrication of nanometer scale semiconductor devices is increasing further and further. But for the nanoscale devices, conventional plasma etching technique is extremely difficult to meet the requirement of the device fabrication, therefore, other etching techniques such as use of multi frequency plasma, source/bias/gas pulsing, etc. are investigated to meet the etching target. Until today, various pulsing techniques including pulsed plasma source and/or pulse-biased plasma etching have been tested on various materials. In this review, the experimental/theoretical studies of pulsed plasmas during the nanoscale plasma etching on etch profile, etch selectivity, uniformity, etc. have been summarized. Especially, the researches of pulsed plasma on the etching of silicon, $SiO_2$, and magnetic materials in the semiconductor industry for further device scaling have been discussed. Those results demonstrated the importance of pulse plasma on the pattern control for achieving the best performance. Although some of the pulsing mechanism is not well established, it is believed that this review will give a certain understanding on the pulsed plasma techniques.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.74-74
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• 2009

The ArF PR mask was. developed to overcome the limit. of sub 40nm patterning technology with KrF PR. But ArF PR difficult to meet the required PR selectivity by thin PR thickness. So need to the multi-stack mask such as amorphous carbon layer (ACL). Generally capacitively coupled plasma (CCP) etcher difficult to make the high density plasma and inductively coupled plasma (ICP) type etcher is more suitable for multi stack mask etching. Hybrid Coupled Plasma source (HCPs) etcher using the 13.56MHz RF power for ICP source and 2MHz and 27.12MHz for bias power was adopted to improve the process capability and controllability of ion density and energy independently. In the study, the oxide trench which has the multi stack layer process was investigated with the HCPs etcher (iGeminus-600 model DMS Corporation). The results were analyzed by scanning electron microscope (SEM) and it was found that etching characteristic of oxide trench profile depend on the multi-stack mask.

• Journal of Information Display
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• v.2 no.4
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• pp.1-7
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• 2001

This paper investigates the characteristics of a newly developed high density hollow cathode plasma(HCP) system and its application for the etching of silicon wafers. We used $SF_6$ and $O_2$ gases in the HCP dry etch process. This paper demonstrates very high plasma density of $2{\times}10^{12}cm^{-3}$ at a discharge current of 20 rna, Silicon etch rate of 1.3 ${\mu}m$/min was achieved with $SF_6/O_2$ plasma conditions of total gas pressure of 50 mTorr, gas flow rate of 40 seem, and RF power of200W. This paper presents surface etching characteristics on a crystalline silicon wafer and large area cast type multicrystlline silicon wafer. We obtained field emitter tips size of less than 0.1 ${\mu}m$ without any photomask step as well as with a conventional photolithography. Our experimental results can be applied to various display systems such as thin film growth and etching for TFT-LCDs, emitter tip formations for FEDs, and bright plasma discharge for PDP applications. In this research, we studied silicon etching properties by using the hollow cathode plasma system.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.363-363
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• 2008

The development of dry etching process for sapphire wafer with plasma has been key issues for the opto-electric devices. The challenges are increasing control and obtaining low plasma induced-damage because an unwanted scattering of radiation is caused by the spatial disorder of pattern and variation of surface roughness. The plasma-induced damages during plasma etching process can be classified as impurity contamination of residual etch products or bonding disruption in lattice due to charged particle bombardment. Therefor, fine pattern technology with low damaged etching process and high etch rate are urgently needed. Until now, there are a lot of reports on the etching of sapphire wafer with using $Cl_2$/Ar, $BCl_3$/Ar, HBr/Ar and so on [1]. However, the etch behavior of sapphire wafer have investigated with variation of only one parameter while other parameters are fixed. In this study, we investigated the effect of pressure and other parameters on the etch rate and the selectivity. We selected $BCl_3$ as an etch ant because $BCl_3$ plasmas are widely used in etching process of oxide materials. In plasma, the $BCl_3$ molecule can be dissociated into B radical, $B^+$ ion, Cl radical and $Cl^+$ ion. However, the $BCl_3$ molecule can be dissociated into B radical or $B^+$ ion easier than Cl radical or $Cl^+$ ion. First, we evaluated the etch behaviors of sapphire wafer in $BCl_3$/additive gases (Ar, $N_2,Cl_2$) gases. The behavior of etch rate of sapphire substrate was monitored as a function of additive gas ratio to $BCl_3$ based plasma, total flow rate, r.f. power, d.c. bias under different pressures of 5 mTorr, 10 mTorr, 20 mTorr and 30 mTorr. The etch rates of sapphire wafer, $SiO_2$ and PR were measured with using alpha step surface profiler. In order to understand the changes of radicals, volume density of Cl, B radical and BCl molecule were investigated with optical emission spectroscopy (OES). The chemical states of $Al_2O_3$ thin films were studied with energy dispersive X-ray (EDX) and depth profile anlysis of auger electron spectroscopy (AES). The enhancement of sapphire substrate can be explained by the reactive ion etching mechanism with the competition of the formation of volatile $AlCl_3$, $Al_2Cl_6$ or $BOCl_3$ and the sputter effect by energetic ions.

• Journal of the Speleological Society of Korea
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• no.82
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• pp.1-4
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• 2007

In this paper, the etching of Au films using photoresist masks on Si substrates was investigated using a capacitively coupled plasma etch reactor. The advantages of plasma etch techniques over current methods for Au metalization include the ability to simplify the metalization process flow with respect to resist lift-off schemes, and the ability to cleanly remove etched material without sidewall redeposition, as is seen in ion milling. The etch properties were measured for different gas mixing ratios of CF4/Ar, and chamber pressures while the other conditions were fixed. According to statistical design of experiment (DOE), etching process of Au films was characterized and also 20 samples were fabricated followed by measuring etch rate, selectivity and etch profile. There is a chemical reaction between CF4 and Au. Au- F is hard to remove from the surface because of its high melting point. The etching products can be sputtered by Ar ion bombardment.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.519-522
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• 2002

In this paper, we analyze the impact of plasma etching process induced device degradation on low temperature poly-Si TFTs. The results indicate the relationship between device degradation and PPID effect during plasma fabrication. The dual-gate structure, which is used to suppress leakage current, is also discussed in this research.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.1485-1488
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• 1997

The capacity of memory chip has increased vert quickly and 64MDRAM becomes main product in semiconductor manufacturing lines consists of many sequential processes, including etching process. although it needs direct sensing of wafer state for the accurae detching, it depends on indirect esnsing and sample test because of the complexity of the plasma etching. This equipment receives the inner light of etch chamber through the viewport and convets it to the voltage inetnsity. In this paper, EDP voltage signal has a new role to detect etching failure. First, we gathered data(EPD sigal, etching time and etchrate) and then analyzed the relationships between the signal variatin and the etch rate using two neural network modeling. These methods enable to predict whether ething state is good or not per wafer. For experiments, it is used High Density Inductive coupled Plasma(HDICP) ethcing equipment. Experiments and results proved to be abled to determine the etching state of wafer on-line and analyze the causes by modeling and EPD signal data.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1045-1048
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• 2003

In this paper, we studied plasma damage of MIS capacitor with $Al_2$O$_3$ dielectric film. Using capacitor pattern with the same area but different perimeters, we tried to separate etching damage mechanism and to optimize the dry etching process. After etching both metal and dielectric layer by the same condition, leakage current and C-V measurements were carried out for Pt/A1$_2$O$_3$/Si structures. The flatband voltage shift was appeared in the C-V plot, and it was caused by the variation of the fixed interface charge and the interface trapped charge. From I-V measurement, it was found the leakage current along the periphery could not be ignored. Finally, we established the process condition of RF power 300W, 100mTorr, Ar/Cl$_2$ gas 60sccm as an optimal etching condition.

• Proceedings of the Korean Nuclear Society Conference
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• 1996.11b
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• pp.506-511
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• 1996

Research on the dry etching of UO$_2$ by using fluorine containing gas plasma is carried out for DUPIC (Direct Use of spent PWR fuel In CANDU) process which is taken into consideration for potential future fuel cycle in Korea. CF$_4$/O$_2$ gas mixture is chosen for the reactant gas and the etching rates of UO$_2$ by the gas plasma are investigated as functions of substrate temperature, plasma gas pressure, CF$_4$/O$_2$ ratio, and plasma power, It is tentatively found that the etching rate can reach 1000 monolayers/min. and the optimum CF$_4$/O$_2$ ratio is around 4:1.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1448-1449
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• 2006

Pb(Zr,Ti)$O_3$ is one of the most attractive ferroelectric materials for realizing the FeRAM due to its higher remanant polarization and the ability to withstand higher coercive fields. Generally, the ferroelectric materials were patterned by a plasma etching process for high-density FeRAM. The applicable possibility of CMP process to pattern Pb(Zr,Ti)$O_3$ instead of plasma etching process was investigated in our previous study for improvement of an angled sidewall which prevents the densification of ferroelectric memory and is apt to receive the plasma damage. Our previous study showed that good removal rate with the excellent surface roughness compared to plasma etching process were obtained by CMP process for the patterning of Pb(Zr,Ti)$O_3$. The suitable selectivity to TEOS without any damage to the structural property of Pb(Zr,Ti)$O_3$ was also guaranteed. In this study, the removal mechanism of $Pb_{1.1}(Zr_{0.52}Ti_{0.48})O_3$ coated by sol-gel method was investigated. Surface analysis of polished specimens at the best and worst conditions was carried out by XPS.