• Proceedings of the KIEE Conference
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• 1998.07g
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• pp.2515-2517
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• 1998

The micro fresnel lens(MFL) was modeled and fabricated on a XY-stage electrostatically driven by comb actuator. The modeled MFL was approximated as a step shape with 4-phase and 4-zone plate. The focal length and diameter of the MFL is 20mm and 912${\mu}m$, respectively. The XY-stage suspending the MFL is designed to generate a large static displacement up to about 20${\mu}m$. On SOI substrates, we first fabricated MFL using the RIE(reactive Ion etching) technology and then patterned and etched bulk silicon to make XY-stage. After the fabrication of all structures on top side of the SOI substrates. $Si_3N_4$ was deposited for passivation of all structures using PECVD(plasma enhanced chemical vapor deposition). All the MFL systems width comb drive actuator were released by KOH etching from the bottom side of the SOI wafer using double-sided alignment technique. In fabrication of MFL, a dry etching conditions is established in order to improve surface roughness and to control the etched depth.

• Journal of the Semiconductor & Display Technology
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• v.13 no.4
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• pp.15-20
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• 2014

The fracture analysis of $SiN_x$ layers, which were deposited by low-temperature plasma enhanced chemical vapor deposition (LT-PECVD) and could be used for an encapsulation layer of a flexible organic light emitting display (OLED), was performed by an electrical method. The specimens of metal-insulator-metal (MIM) structure were prepared using Pt and ITO electrodes. We stressed MIM specimen mechanically by bending outward with a bending radius of 15mm repeatedly and measured leakage current through the top and bottom electrodes. We also observed the cracks, were generated on surface, by using optical microscope. Once the cracks were initiated, the leakage current started to flow. As the amount of cracks increased, the leakage current was also increased. By correlating the electrical leakage current in the MIM specimen with the bending times, the amount of cracks in the encapsulation layer, generated during the bending process, was quantitatively estimated and fracture behavior of the encapsulation layer was also closely investigated.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2006.10a
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• pp.4-5
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• 2006

This paper represents modeling and optimization techniques for solar cell process on single-crystalline float zone (FZ) wafers with high efficiency; There were the four significant processes : i)emitter formation by diffusion, anti-reflection-coating (ARC) with silicon nitride using plasma-enhanced chemical vapor deposition (PECVD); iii)screen-printing for front and back metallization; and iv)contact formation by firing. In order to increase the performance of solar cells, the contact formation process is modeled and optimized. This paper utilizes the design of experiments (DOE) in contact formation to reduce process time, fabrication costs. The experiments were designed by using central composite design which is composed of $2^4$ factorial design augmented by 8 axial points with three center points. After contact formation process, the efficiency of the solar cell is modeled using neural networks. This model is used to analyse the characteristics of the process, and to optimize the process condition using genetic algorithms (GA). Finally, find optimal recipe for solar cell efficiency.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.9
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• pp.766-772
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• 2011

Amorphous Si (a-Si) thin films of $p^+/p^-/n^+$ were deposited on $Si_3N_4$/glass substrate by using a plasma enhanced chemical vapor deposition (PECVD) method. These films were annealed at various temperatures and for various times by using a rapid thermal process (RTP) equipment. This step was added before the main thermal treatment to make the nuclei in the a-Si thin film for reducing the process time of the crystallization. The main heat treatment for the crystallization was performed at the same condition of $600^{\circ}C$/18 h in conventional furnace. The open-circuit voltages ($V_{oc}$) were remained about 450 mV up to the nucleation condition of 16min in the nucleation RTP temperature of $680^{\circ}C$. It meat that the process time for the crystallization step could be reduced by adding the nucleation step without decreasing the electrical property of the thin film Si for the solar cell application.

• Transactions of the Korean Society of Automotive Engineers
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• v.23 no.6
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• pp.656-662
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• 2015

In the present study, multi-layered Si DLC (Silicon Diamond-Like Carbon) coatings with HMDSO (Hexamethyldisiloxane) buffer layers are applied on SKD 11 substrates by PECVD (Plasma Enhanced Chemical Vapor Deposition) with different HMDSO gas flow rates, while the gas flow rate of $C_2H_2$ is fixed to enhance the electric resistivity of forming dies for electrically assisted forming. The HMDSO buffer layer is introduced to increase adhesion between the base metal and Si-DLC layers. The result of evaluation of electric resistivity and adhesion strength shows that the properties are affected by the flow rate of HMDSO, while the flow rate of 80 sccm results in the coating with the highest electric resistivity and adhesion strength among the selected flow rates.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.323-323
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• 2010

Saw damage of crystalline silicon wafer is unavoidable factor. Usually, alkali treatment for removing the damage has been carried out as the saw damage removal (SDR) process for priming the alkali texture. It usually takes lots of time and energy to remove the sawed damages for solar grade crystalline silicon wafers We implemented two different mixed acidic solution treatments to obtain the improved surface structure of silicon wafer without much sacrifice of the silicon wafer thickness. At the first step, the silicon wafer was dipped into the mixed acidic solution of $HF:HNO_3$=1:2 ration for polished surface and at the second step, it was dipped into the diluted mixed acidic solution of $HF:HNO_3:H_2O$=7:3:10 ratio for porous structure. This double treatment to the silicon wafer brought lower reflectance (25% to 6%) and longer carrier lifetime ($0.15\;{\mu}s$ to $0.39\;{\mu}s$) comparing to the bare poly-crystalline silicon wafer. With optimizing the concentration ratio and the dilution ratio, we can not only effectively substitute the time consuming process of SDR to some extent but also skip plasma enhanced chemical vapor deposition (PECVD) process. Moreover, to conduct alkali texture for pyramidal structure on silicon wafer surface, we can use only nitric acid rich solution of the mixed acidic solution treatment instead of implementing SDR.

• Design & Manufacturing
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• v.15 no.3
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• pp.7-12
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• 2021

Plastic injection molds used for rapid heating and cooling must minimize surface damage due to friction and maintain excellent thermal and low electrical conductivity. Accordingly, various surface treatments are being applied. The properties of Al₂O₃ coating and DLC coating were compared to find the optimal surface treatment method. Al₂O₃ coating was deposited by thermal spray method. DLC films were deposited by sputtering process in room temperature and high temperature PECVD (Plasma enhanced chemical vapor deposition) process in 723 K temperature. For the evaluation of physical properties, the electrical and thermal conductivity including surface hardness, adhesion and wear resistance were analyzed. The electrical resistance of the all coated samples was showed insulation properties of 24 MΩ/sq or more. Especially, the friction coefficient of high temp. DLC coating was the lowest at 0.134.

• Journal of the Korean Vacuum Society
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• v.10 no.1
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• pp.104-111
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• 2001

B-doped hydrogenated amorphous silicon carbide (a-SiC:H) thin films were prepared by plasma-enhanced chemical-vapor deposition in a gas mixture of $SiH_4, CH_4,\;and\; B_2H_6$. Physical and chemical properties of a-SiC:H films grown with varing the ratio of $B_2H_6/(SiH_4+CH_4)$ were characterized with various analysis methods including scanning electron microscopy (SEM), X-ray diffractometry (XRD), Raman spectroscopy, Fourier-transform infrared (FTIR) spectroscopy, secondary ion mass spectroscopy (SIMS), UV absorption CH_4spectroscopy and electrical conductivity measurements. With the B-doping concentration, the doping efficiency and the micro-crystallinity were decreased and the film became amorphous when $B_2H_6/(SiH_4{plus}CH_4)$ was over $5{\times}10^{-3}$. The addition of $B_2H_6$ gas during deposition decreased the H content in the film by lowering the quantity of Si-C-H bonds. Consequently, the optical band gap and the activation energy of a-SiC:H films were decreased with increasing the B-doping level.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.538-539
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• 2013

여러 장점으로 인해 OLED는 디스플레이 및 조명 등 적용분야가 넓어지고 있지만, 수분 및 산소에 취약하여 그 수명이 제한되는 단점이 있다. 이를 해결하고자 현재까지는 glass cap을 이용한 encapsulation 기술이 적용되고 있지만, flexible 기판에 적용하지 못하는 문제가 있다. 이러한 문제를 해결하고자 여러 가지 thin film encapsulation 기술이 적용되고 있으나 보다 신뢰성이 높은 기술의 개발이 절실한 때이다. Encapsulation 무기 박막 물질로서 $Si_3N_4$ 박막은 PE-CVD (Plasma Enhanced Chemical Vapor Deposition) 등의 박막 증착법을 사용한 많은 연구가 진행되어, 저온에서의 좋은 품질의 박막 증착이 가능하지만, 100도 이하의 thermal budget을 갖는 OLED Encapsulation에 사용하기에는 충분하지 않았다. CVD 박막의 특성을 더욱 개선하기 위해 최근 ALD (Atomic Layer Deposition) 방법을 통한 $Al_2O_3$ film 증착 방법이 연구되고 있지만, 낮은 증착 속도로 인해 양산에 걸림돌이 되고 있다. 본 연구에서는 또 다른 해결책으로서 Digital CVD 방법을 이용한 양질의 $Si_3N_4$ 박막의 증착을 연구하였다. 이것은 ALD 증착법과 유사하며, 1st step에서 PECVD 방법으로 4~5 ${\AA}$의 얇은 silicon 박막을 증착하고, 2nd step에서 nitrogen plasma를 이용하여 질화 반응을 진행하고, 이러한 cycle을 원하는 두께가 될 때까지 반복적으로 진행된다. 이 때 1 cycle 당 증착속도는 7 ${\AA}$/cycle 정도였다. 최적의 증착 방법과 조건으로 기존의 CVD $Si_3N_4$ 박막 대비 1/5 이하로 pinhole을 최소화 할 수는 있지만 완벽하게 제거하기는 힘든 문제가 있고, 이를 해결하기 위한 개선을 위한 접근 방법이 필요하다고 판단하였다. 본 연구에서는 무기물 박막인 carbon nitride를 이용한 SiN/C:N multilayer 증착 연구를 진행하였다. Fig. 1은 CVD 조건으로 증착된 두께 750 nm SiN film에서 여러 층의 C:N film layer를 삽입했을 때, 38 시간의 85%/$85^{\circ}C$ 가속실험에 따라 OLED의 발광 사진이다. 그림에서 볼 수 있듯이 C:N 층을 삽입하고 또한 그 박막의 수가 증가함에 따라서 OLED에 대한 encapsulation 특성이 크게 개선됨을 확인할 수 있다.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.434-435
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• 2012

Plasma enhanced chemical vapor deposition (PECVD) silicon dioxide thin films have many applications in semiconductor manufacturing such as inter-level dielectric and gate dielectric metal oxide semiconductor field effect transistors (MOSFETs). Fundamental chemical reaction for the formation of SiO2 includes SiH4 and O2, but mixture of SiH4 and N2O is preferable because of lower hydrogen concentration in the deposited film [1]. It is also known that binding energy of N-N is higher than that of N-O, so the particle generation by molecular reaction can be reduced by reducing reactive nitrogen during the deposition process. However, nitrous oxide (N2O) gives rise to nitric oxide (NO) on reaction with oxygen atoms, which in turn reacts with ozone. NO became a greenhouse gas which is naturally occurred regulating of stratospheric ozone. In fact, it takes global warming effect about 300 times higher than carbon dioxide (CO2). Industries regard that N2O is inevitable for their device fabrication; however, it is worthwhile to develop a marginable nitrous oxide free process for university lab classes considering educational and environmental purpose. In this paper, we developed environmental friendly and material cost efficient SiO2 deposition process by substituting N2O with O2 targeting university hands-on laboratory course. Experiment was performed by two level statistical design of experiment (DOE) with three process parameters including RF power, susceptor temperature, and oxygen gas flow. Responses of interests to optimize the process were deposition rate, film uniformity, surface roughness, and electrical dielectric property. We observed some power like particle formation on wafer in some experiment, and we postulate that the thermal and electrical energy to dissociate gas molecule was relatively lower than other runs. However, we were able to find a marginable process region with less than 3% uniformity requirement in our process optimization goal. Surface roughness measured by atomic force microscopy (AFM) presented some evidence of the agglomeration of silane related particles, and the result was still satisfactory for the purpose of this research. This newly developed SiO2 deposition process is currently under verification with repeated experimental run on 4 inches wafer, and it will be adopted to Semiconductor Material and Process course offered in the Department of Electronic Engineering at Myongji University from spring semester in 2012.