• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2000년도 제1회 학술대회 논문집
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• pp.15-16
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• 2000

The gate bias stress effect of the hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) with a $SiN_x/BCB$ gate insulator have been studied. The gate planarization was carried out by spin-coating of BCB (benzocyclobutene) on Cr gates. The BCB exhibits charge trappings during a high gate bias, but the stability of the TFT is the same as conventional one when it is between -25 V and +25 V. The charge trap density in the BCB increases with its thickness.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 추계학술대회 논문집 Vol.15
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• pp.178-181
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• 2002

We studied the characteristics of polishing pad, which can apply W CMP process for global planarization of multilevel interconnection structure. Also we investigated the effects of different sets of polishing pad. The purpose of this experiment is the cost reduction by the increase of pad life time and decrease of cycle time and slurry usage with new pad. Especially we studied the effect of polishing pad for CMP process by this experiment of polishing pad that is consumables material during CMP process. We expecting the increase of process throughput and improvement of device manufacturing yield because we can choose optimum polishing pad through this result.

• 한국세라믹학회지
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• 제23권4호
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• pp.55-61
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• 1986

Phosphosilicate glass(PSG) films have been used as fusable deposited dielectrics in silicon gate MOS integrated circuits. But in this experiment BPSG(borophosphosilicate glass) will be optimized for more efficient utilization of the reactants. The BPSG films were deposited on silicon wafers by the oxidation of the hydrides at 430$^{\circ}$C in conventional atmospheric-pressure chemical-vapor-deposition (CVD) systems. Physical and chemical properties of CVD BPSG films have been characterized both for as-deposited and for fused films The. relationship between deposited BPSG film composition and infra-red absorption solution etch rate and fusion temperature is discussed and examples of BPSG composition that can be fused at 900~95$0^{\circ}C$ and 800~85$0^{\circ}C$ are given. In addition to having lower fusion temperature than PSG films BPSG films have lower as-deposited intrinsic tensile stress and low aqueous chemical etch rate they have been considered for applications where these characteristics are advantageous.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(I)
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• pp.561-564
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• 1987

The deposition and reflow properties or BPSG film deposited by APCVD was characterized by variation of each process parameter. As deposition temperature is increased higher, deposition rate is decreased. Maximum deposition rate of BPSG film is obtained in higher 02/Hyride ratio than CVD Oxide or PSG. BPSG film shows stable dielectric properties and we obtained good planarization effect at lower reflow temperature in case of BPSG film than PSG film.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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• pp.389-392
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• 2004

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. The effect of alternative commerical slurries pads, and post-CMP cleaning alternatives are discuess, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. we investigated the performance of $SnO_2$-CMP process using commonly used silica slurry, ceria slurry, tungsten slurry. This study shows removal rate and non-uniformity of $SnO_2$ thin film used to gas sensor by using Ceria, Silica, W-Slurry after CMP process. This study also shows the relation between particle size and CMP with particle size analysis of used slurry.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 추계학술대회 논문집 Vol.16
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• pp.184-187
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• 2003

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD) lyaer with free-defect. The effect of alternative commerical slurries pads, and post-CMP cleaning alternatives are discuess, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. we investigated the performance of $SnO_2-CMP$ process using commonly used silica slurry, ceria slurry, tungsten slurry. This study shows removal rate and nonuniformity of $SnO_2$ thin film used to gas sensor by using Ceria, Silica, W-Slurry after CMP process. This study also shows the relation between partical size and CMP with partical size analysis or used slurry.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제53권3호
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• pp.128-132
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• 2004

The perovskite ferroelectric materials of the PZT, SBT and BST series will attract much attention for application to ULSI devices. Among these materials, the BST ($Ba_0.6$$Sr_0.4$/$TiO_3$) is widely considered the most promising for use as an insulator in the capacitors of DRAMS beyond 1 Gbit and high density FRAMS. Especially, BST thin films have a good thermal-chemical stability, insulating effect and variety of Phases. However, BST thin films have problems of the aging effect and mismatch between the BST thin film and electrode. Also, due to the high defect density and surface roughness at grain boundarys and in the grains, which degrades the device performances. In order to overcome these weakness, we first applied the chemical mechanical polishing (CMP) process to the polishing of ferroelectric film in order to obtain a good planarity of electrode/ferroelectric film interface. BST ferroelectric film was fabricated by the sol-gel method. And then, we compared the surface characteristics before and after CMP process of BST films. We expect that our results will be useful promise of global planarization for FRAM application in the near future.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2003년도 춘계학술대회 논문집
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• pp.86-89
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• 2003

Chemical Mechanical Planarization(CMP) has been accepted as the most effective processes for ultra large scale integrated (ULSI) chip manufacturing. However, as the polishing process continues, pad pores get to be glazed by polishing residues, which hinder the supply of new slurry. And pad surface is ununiformly deformed as real contact distance. These defects make material removal rate(MRR) decrease with a number of polishied wafer. Also the desired within-chip planarity, within wafer non-uniformity(WIWNU) and wafer to wafer non-uniformity(WTWNU) arc unable to be achieved. So, pad conditioning in CMP Process is essential to overcome these defects. The eletroplated or brazed diamond conditioner is used as the conventional conditioning. And. allumina long fiber, the jet power of high pressure deionized water, vacuum compression. ultrasonic conditioner aided by cavitation effect and ceramic plate conditioner are once used or under investigation. But. these methods arc not sufficient for ununiformly deformed pad surface and the limits of conditioning effect. So this paper focuses on the characteristics of diamond conditioner which reopens glazed pores and removes ununiformly deformed pad away.

• 한국재료학회지
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• 제18권6호
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• pp.334-338
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• 2008

The purpose of this study is to characterize various electrolytes on electrochemical mechanical planarization (ECMP). The ECMP system was modified from conventional CMP system to measure the potentiodynamic curve and removal rate of Cu. The potentiodynamic curves were measured in static and dynamic states in investigated electrolytes using a potentiostat for the evaluation of the polishing behavior on ECMP. KOH (alkaline) and $NaNO_3$ (salt) were selected as electrolytes which have high conductivity. In static and dynamic states, the corrosion potential decreased and the corrosion current increased as a function of the electrolyte concentration. But, the electrochemical reaction was prevented by mechanical polishing effect in the dynamic state. The static etch and removal rate were measured as functions of concentration and applied voltage. When $NaNO_3$ was used, the dissolution was much faster than that of KOH. It was concluded that the removal rate was strongly depended on electrochemical dissolution. The removal rate increased up to 350 nm/min in $NaNO_3$ based electrolyte.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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• pp.20-23
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• 2004

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing(CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. However, as the IMD layer gets thinner, micro-scratches are becoming as major defects. Chemical-Mechanical polishing(CMP) of conductors is a key process in Damascene patterning of advanced interconnect structure. The effect of alternative commercial slurries pads, and post-CMP cleaning alternatives are discuss, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. Electroplated copper deposition is a mature process from a historical point of view, but a very young process from a CMP perspective. While copper electro deposition has been used and studied for decades, its application to Cu damascene wafer processing is only now gaining complete acceptance in the semiconductor industry. The polishing mechanism of Cu-CMP process has been reported as the repeated process of passive layer formation by oxidizer and abrasion action by slurry abrasives. however it is important to understand the effect of oxidizer on copper passivation layer in order to obtain higher removal rate and non-uniformity during Cu-CMP process. In this paper, we investigated the effects of oxidizer on Cu-CMP process regarding the additional volume of oxidizer.