• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2008년도 추계종합학술대회 B
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• pp.571-574
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• 2008

본 논문에서는 개선된 회로를 적용한 $256{\times}256$ 픽셀 저항형 지문센서를 제안하고 있다. 단위 픽셀 수준의 센싱 회로는 가변적인 전류를 전압으로 변환하여 이진 디지털 신호로 만든다. 정전기에 효과적으로 대처할 수 있는 인접 픽셀 간 전기적 차폐 레이아웃 구조를 제안하고 있다. 전체회로는 단위 센서 회로를 확장하여 ASIC 설계방식을 통하여 설계한 뒤 로직 및 회로에 대하여 모의실험을 하였다. 전체회로는 $0.35{\mu}m$ 표준 CMOS 공정규칙을 적용하여 센서블록은 전주문 방식을 적용하고 전체 칩은 자동배선 틀을 이용하여 반주문 방식으로 레이아웃을 실시하였다.

• 센서학회지
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• 제18권6호
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• pp.475-484
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• 2009

In this paper, an analysis of the complementary CMOS active pixel and readout circuit is carried out. Complementary pixel structure which is different from conventional 3TR APS structure consists of photo diode, reset PMOS, several NMOSs and PMOSs sets for complementary signals. Proposed CMOS image sensors pixel has been fabricated using 0.5 standard CMOS process. Measured results show that the output signal range is from 0.8 V to 3.8 V. This output signal range increased 125 % compared to conventional 3TR pixel in the condition of 5 V power supply.

• 센서학회지
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• 제23권2호
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• pp.87-93
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• 2014

In this paper, we propose a block-based low-power complementary metal oxide semiconductor (CMOS) image sensor (CIS) with a simple pixel structure for power efficiency. This method, which uses an additional computation circuit, makes it possible to reduce the power consumption of the pixel array. In addition, the computation circuit for a block-based CIS is very flexible for various types of pixel structures. The proposed CIS was designed and fabricated using a standard CMOS 0.18 ${\mu}m$ process, and the performance of the fabricated chip was evaluated. From a resultant image, the proposed block-based CIS can calculate a differing contrast in the block and control the operating voltage of the unit blocks. Finally, we confirmed that the power consumption in the proposed CIS with a simple pixel structure can be reduced.

• 센서학회지
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• 제21권1호
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• pp.7-12
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• 2012

In this paper, we propose a 4-transistor active pixel sensor(APS) with a novel correlated double sampling(CDS) circuit for the purpose of extending dynamic range. Dual sampling techniques can overcome low-sensitivity and temporal disparity problems at low illumination. To accomplish this, two images are obtained at the same time using different sensitivities. The novel CDS circuit proposed in this paper contains MOS switches that make it possible for the capacitance of a conventional CDS circuit to function as a charge pump, so that the proposed APS exhibits an extended dynamic range as well as reduced noise. The designed circuit was fabricated by using $0.35{\mu}m$ 2-poly 4-metal standard CMOS technology and its characteristics have been evaluated.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2004년도 ICCAS
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• pp.1235-1238
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• 2004

Thresholding has been used to reduce the number of gray values in images. Typically, a single threshold value has been used, resulting in two gray level images. Image reduction of one single threshold value, however, may lose too much of the high-frequency edge information. Thus, dynamic thresholding that uses a different threshold for each pixel is preferred instead of using a single threshold value. Dynamic thresholding can preserve high frequency details as well as reduce the size of images. Since it takes long time to perform existing software dynamic thresholding in an embedded system, this paper proposes and implements a circuit by using a FPGA in order to perform a real-time dynamic thresholding,. The proposed circuit consists of two counters, and threshold look-up table, and control unit. The values of two counters determine each pixel position, the threshold look-up table converts each pixel value into other value, and the control unit generates necessary control signals. On arriving from a camera to the proposed circuit, each pixel is compared with its threshold value and is converted into other gray value. An image processing system by using the proposed circuit will be implemented and some experiments will be performed.

• 전자공학회논문지
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• 제52권11호
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• pp.36-43
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• 2015

본 연구를 통해서 초점면 배열 이차원 마이크로볼로미터를 위한 픽셀 단위의 신호취득 회로를 연구하였다. 높은 응답도와 긴 적분시간을 갖는 픽셀 단위의 구조를 위해 이 단계 바이어스 전류 억제 방식을 갖는 전류 미러 입력회로를 제안하였다. 제안하는 회로는 $0.35-{\mu}m$ 2-poly 4-metal CMOS 공정을 이용하여 설계했고, 마이크로볼로미터의 배열 크기는 $320{\times}240$이며 픽셀 크기는 $50{\mu}m{\times}50{\mu}m$이다. 제안하는 이 단계 바이어스 전류 억제 방식은 넓은 보정 범위에서 충분히 작은 보정 오차를 보이며, 설계 파라미터를 조정하여 보정 범위와 보정 오차를 간단히 최적화할 수 있다. 제안하는 회로는 높은 응답도와 1 ms 이상의 긴 적분시간을 갖기 때문에 회로의 잡음등가온도차(NETD)를 26 mK까지 개선할 수 있고, 이는 기존회로의 잡음등가 온도차인 67 mK에 비해 매우 개선된 수치이다.

• 대한전자공학회논문지SD
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• 제41권9호
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• pp.49-56
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• 2004

HgCdTe 64×2 중원적외선 이중대역 동시검출기를 위한 포화전류차단 회로를 갖는 BDI입력방식의 신호취득회로(ROIC)를 설계하였다. 제안된 포화차단 회로를 통해서 중적외선 신호가 포화되면 원적외선 신호도 왜곡이 일어나던 기존의 문제점을 해결함으로써 120k정도 더 넓은 온도 영역의 물체까지 측정할 수 있는 범위를 확보하고 중적외선 검출기에서 발생하는 dead pixel에 의해 원적외선 검출기의 성능은 영향받지 않는 특성을 보였다. 회로 제작에 사용한 공정은 0.Sum 2-poly 3-metal Hynix CMOS 공정이었다. 측정결과 중적외선 신호와 원적외선 신호가 동시에 처리되는 것을 확인할 수 있었다. 또한, 측정된 잡음의 크기는 상온에서 53uV로서 동작온도 77K의 값으로 환산시켜 보았을 때 27uV로 ROIC의 특성이95% BLIP 조건을 만족함을 알 수 있었다.

• 한국전기전자재료학회논문지
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• 제20권3호
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• pp.250-256
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• 2007

We analyzed the effect of a pixel and all the inter-electrode capacitances in a unit pixel of TFT-LCDs on the gray scale capability. The pixel and all the inter-electrode parasitic capacitances were obtained from the tree dimensional profiles of potential distribution and molecular director considering lateral fields generated at the edge of the pixel. To obtain the RMS and kickback voltages of the pixel, we constructed an equivalent circuit of the panel containing all the parasitic capacitances. The calculation was performed though H-SPICE. As results, we confirmed that the pixel becomes smaller, the effect of parasitic capacitances on the gray scale capability becomes larger.

• ETRI Journal
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• 제34권4호
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• pp.633-636
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• 2012

A dynamic analysis of an amorphous silicon (a-Si) thin film transistor liquid crystal display (TFT-LCD) pixel is presented using new a-Si TFT and liquid crystal (LC) capacitance models for a Simulation Program with Integrated Circuit Emphasis (SPICE) simulator. This dynamic analysis will be useful when predicting the performance of LCDs. The a-Si TFT model is developed to accurately estimate a-Si TFT characteristics of a bias-dependent gate to source and gate to drain capacitance. Moreover, the LC capacitance model is developed using a simplified diode circuit model. It is possible to accurately predict TFT-LCD characteristics such as flicker phenomena when implementing the proposed simulation model.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.466-469
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• 2009

The life time of AMOLED displays has been dependent on OLED materials up to this point. In particular, image sticking (burn-in) has been one of the most critical issues for AMOLEDs. This paper proposes image sticking compensation AMOLED pixel circuits to address the problem without requiring process or material improvements to the OLED itself. We verified the performance of those circuits by simulation and actual panel implementation.