• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.579-582
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• 2002

We developed three kinds of electrode-structures for high luminance and luminous efficiency. Also, we optimized the mixture gas. Three kinds of 7.5-inch experimental panels having a pixel pitch of 0.864mm were evaluated, and high efficiency of 1.6lm/W was obtained in the panel type2.

• Current Optics and Photonics
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• v.1 no.2
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• pp.150-156
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• 2017

A diffraction limited optical system for head mounted displays (HMDs) was designed. This optical system consists of four modules, including 1:5 mm and 5:30 mm beam expanders, polarization grating-polarization conversion system (PG-PCS) and refractive/diffractive projection optical module. The PG-PCS module transforms the unpolarized Gaussian beam to a linearly polarized beam and it simultaneously homogenizes the spatial intensity profile. The optical projector module has a $30^{\circ}$ field of view, a 22 mm eye relief, and a 10 mm exit pupil diameter with a compact structure. Common acrylic materials were utilized in the optical design process; therefore, the final optical system was lightweight. The whole optical system is suitable for a 0.7 inch liquid crystal on silicon microdisplay (LCOS) with HDTV resolution ($1920{\times}1080$) and $8.0{\mu}m$ pixel pitch.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.235-236
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• 2007

CCD(Charge-Coupled Device) 혹은 CMOS (Complementary Metal Oxide Semiconductor)와 같은 소자를 이용하여 빛을 전기적 신호인 Image로 재구성하는 촬상소자(Color Capture Device)는 촬영환경이 어두워지면 Dynamic Range가 작아지고, Noise가 상대적으로 심해진다[1][2]. 본 논문에서는 촬영 환경이 어두울 때, Resolution을 Preserving하는 Pixel Pitch가 큰 촬상 소자와 Motion Blur를 억제하는 Exposure Time이 긴 촬상 소자의 조합을 신호처리로 구현하여, 신호의 Power를 향상시켜 Dynamic Range를 키우고 Noise의 Boost-up을 억제하여 SNR(Signal to Noise Ratio)을 향상시키는 방식으로, 촬상 장치의 감도를 향상시켜 화질을 개선하는 방법을 제안한다.

• Proceedings of the KSRS Conference
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• 2003.11a
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• pp.286-288
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• 2003

In this paper, we present our implementation of the direct camera model (image to ground) for SPOT5 and use it to assess the geometric accuracy of SPOT5 imagery. Our assessment confirms the location accuracy of SPOT5 imagery (without use of GCPs) is less than 50m. We further introduce a few attitude parameters to refine the camera model with GCPs. The model is applied to two SPOT5 supermode images, one near vertical, incidence angle of 3 degrees, and one far oblique, incidence angle of 27 degrees. The results show that accuracy (rms of check points) of about one pixel (2.5m) can be achieved with about 4 GCPs by using only 3 parameters to correct the yaw, pitch and roll of the satellite.

• Electronics and Telecommunications Trends
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• v.34 no.6
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• pp.145-155
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• 2019

Holography is a technique that can acquire and reproduce 3D objects nearly perfectly by representing both the amplitude and phase of light. Recently, digital holography has received considerable attention because it is simpler than analog holography from acquisition to reproduction. The data size of the digital hologram increases tremendously as the quality of digital holograms depends on their pixel pitch and resolution. Hence, efficient compression is necessary to realize holographic imaging services. In this report, we introduce recent digital hologram compression techniques and JPEG Pleno holography, which is the first international standardization activity for digital hologram compression. Furthermore, we discuss the future of this field.

• Journal of Sensor Science and Technology
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• v.30 no.4
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• pp.223-228
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• 2021

This work presents a low-power CMOS image sensor (CIS) with a multi-column-parallel (MCP) readout structure while focusing on improving its performance compared to previous works. A delta readout scheme that utilizes the image characteristics is optimized for the MCP readout structure. By simply alternating the MCP readout direction for each row selection, additional memory for the row-to-row delta readout is not required, resulting in a reduced area of occupation compared to the previous work. In addition, the bias current of a pre-amplifier in a successive approximate register (SAR) analog-to-digital converter (ADC) changes according to the operating period to improve the power efficiency. The prototype CIS chip was fabricated using a 0.18-㎛ CMOS process. A 160 × 120 pixel array with 4.4 ㎛ pitch was implemented with a 10-bit SAR ADC. The prototype CIS demonstrated a frame rate of 120 fps with a total power consumption of 1.92 mW.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.27-37
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• 1999

A CMOS ReadOut Integrated Circuit (ROlC) for InfraRed Focal Plane Array (IRFPA) detector is presented, which is a key component in uncooled thermal imaging systems. The ROIC reads out signals from $64\times64$ Barium Strontium Titanate (BST) infrared detector array, then outputs pixel signals sequentially after amplifying and noise filtering. Various design requirements and constraints have been considered including impedance matching, low noise, low power dissipation and small detector pitch. For impedance matching between detector and pre~amplifier, a new circuit based on MOS diode structure is devised, which can be easily implemented using standard CMOS process. Also, tunable low pass filter with single~pole is used to suppress high frequency noise. In additions, a clamping circuit is adopted to enhance the signal~to-noise ratio of the readout output signals. The $64\times64$ IRFPA ROIC is designed using $0.65-\mu\textrm{m}$ 2P3M (double poly, tripple metal) N~Well CMOS process. The core part of the chip contains 62,000 devices including transistors, capacitors and resistors on an area of about $6.3-mm\times6.7-mm$.

• Korean Journal of Digital Imaging in Medicine
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• v.6 no.1
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• pp.24-30
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• 2003

Flat-panel detector(FPD) is the driving force for realizing the next gene ration of x-ray system. In this study, we developed amorphous selenium(a-Se) based flat-panel digital X-ray detector(DXD) for radiography. The prototype detector consists of an amorphous selenium layer and a thin-film transistor(TFT) array. Comparing to other papers1)-4), optimization of amorphous selenium and progress of evaporation were similar. The pixel pitch of fabricated detector was $139{\mu}m$, fill factor was 86%, and the size was 14"${\times}$8.5". Hand and test bar pattern images were acquired. A high modulation transfer function(MTF) factor was obtained: 58% at 3.0 lp/mm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.20-27
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• 2011

A CMOS Image Sensor(CIS) mounted on mobile appliances always needs a low power consumption because of the battery life cycle. In this paper, we propose novel power reduction techniques such as a data flip-flop circuit with leakage current elimination, a low power single slope A/D converter with a novel comparator, and etc. Based on 0.13um CMOS process, the chip satisfies QVGA resolution($320{\times}240$ pixels) whose pitch is 2.25um and whose structure is 4-Tr active pixel sensor. From the experimental results, the ADC in the middle of CIS has a 10-b resolution, the operating speed of CIS is 16 frame/s, and the power dissipation is 25mW at 3.3V(Analog)/1.8V(Digital) power supply. When we compare the proposed CIS with conventional ones, the power consumption is reduced approximately by 22% in sleep mode, 20% in operating mode.

• Journal of the Institute of Convergence Signal Processing
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• v.5 no.2
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• pp.165-171
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• 2004

Owing to small sizes and high density to the semiconductor It, it is difficult to discriminate the defects of ICs by human eyes. High precision inspection system with computer vision is essentially established for the manufacturing process due to the variety of defective parts. Especially it is difficult to implement the algorithm for the coplanarity of IC leads. Therefore in this paper, the inspection system which can detect the defects of the SOP types of ICs having 1cm${\times}$0.5cm of the chip size is implemented and evaluated it's performance. In order to optimally detect various items, some principles of geometry are theoretically presented , length measurement, pitch measurement, angle measurement, brightness of image and correcton of position. The interface circuit is designed for implementation of inspection system and connected the HANDLER. In the result, the system could detect two ICs' defects per second and confirmed the resolution of 20$\mu$m per pixel.