• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.3
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• pp.11-23
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• 1995

In this paper, a parallel pipelined processor model which acts as a small VLIW processor architecture and a scheduling algorithm for extracting instruction-level parallelism on this architecture are proposed. The proposed model has a dual-instruction mode which has maximum 4 basic operations being executed in parallel. By combining these basic operations, variable instruction set can be designed for various applications. The scheduling algorithm schedules basic operations for parallel execution and removes pipeline hazards by examining data dependency and resource conflict relations. In order to examine operation and evaluate the performance,a C compiler and a simulator are developed. By simulating various test programs with the compiler and the simulator, the characteristics and the performance result of the proposed architecture are measured.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.6
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• pp.1026-1031
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• 2008

Nowdays, homes and small businesses rely more and more PON(Passive Optical Networks) for financial transactions, private communications and even telemedicine. Thus, encryption for these data transactions is very essential due to the multicast nature of the PON In this parer, we presented our implementation of a counter mode AES based on Virtex4 FPGA. Our design exploits three advanced features; 1) Composite field arithmetic SubByte, 2) efficient MixColumn transformation 3) and on-the-fly key-scheduling for fully pipelined architecture. By pipeling the composite field implementation of the S-box, the area cost is reduced to average 17 percent. By designing the on-the-fly key-scheduling, we implemented an efficient key-expander module which is specialized for a pipelined architecture.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.05a
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• pp.693-694
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• 2014

This paper proposes a new pipelined dynamic bandwidth allocation algorithm for XG-PON (10-Gbps-capable passive optical network) passive optical networks) system. The pipelined algorithm is used when a dynamic bandwidth allocation algorithm cannot finished in an unit time. In the proposed mechanism, the request is immediately transferred to each pipeline block to improve performance.

• Journal of Korea Society of Industrial Information Systems
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• v.4 no.2
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• pp.44-50
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• 1999

This paper presents a set of techniques to automatically find rate optimal or near rate optimal implementation of shift-invariant flow graphs on pipelined processor, in which pipeline processor has multiple accumulators and internal datapaths. In such case, the problem to be addressed is the scheduling of multiple instruction streams which control all of the pipeline stages. The goal of an automatic scheduler in this context is to rearrange the order of instructions such that they are executed with minimum iteration period between successive iteration of defining flow graphs. The scheduling algorithm described in this paper also focuses on the problem of removing the hazards due to inter-instruction dependencies.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.643-646
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• 2005

This paper presents CARMA (Cycle-Accurate Retargetable Micro-Architecture) as efficient framework for SoC-centric pipelined instruction-set architectures. It is based on ADL (Architecture Description Language) and provides more concise and manifest semantics to describe behavior of instruction set by mixing efficiency of instruction-set simulators and flexibility of RTL simulators. It exploits new timing model method based on process scheduling so it can support general timing model with cycle accuracy for large-scaled architectures usually used in SoC multimedia chip-set. According to experiments, the proposed framework was shown to be 5.5 times faster than HDL and 2.5 times faster than System-C in simulation speed so it is applicable for complex instruction-set pipelined architectures.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.148-149
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• 2014

This paper evaluates performance of a pipelined dynamic bandwidth allocation scheme for XG-PON (10-Gbps-capable passive optical network) system for power saving. Under self-similar traffic and balanced input loads, we evaluate performance of XG-PON systems using computer simulations.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.7
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• pp.359-367
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• 2005

This paper presents a scheduling approach for synthesizing pipelined datapaths under resource constraints. The proposed approach evaluates whether or not a scheduling solution can exist in case an operation temporarily is assigned to the earliest or latest control step among the assignable steps for the operation. If a solution cannot be found, it is impossible to assign the operation to that control step due to a violation against resource constraints, and so we can eliminate that control step among candidate assignable control steps. The proposed algorithm builds up a schedule based on gradual mobility reduction and finds a solution that yields high performance by evaluating on the impact on register assignment. Experiments on benchmarks show that this approach gains a considerable improvement over previous approaches.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.149-158
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• 1994

Through high level synthesis, designers can obtain the precious information on the area and speed trade-offs as well as synthesized datapaths from behavioral design descriptions. While previous researches were concentrated on the synthesis of pipelined, datapaths with fixed DII (Data Initiation Interval) by inserting delay elements where needed, we propose a novel methodology of synthesizing pipeline structures with variable DIIs. Determining the time-overlapping of pipeline stages with variable DIIs, the proosed algorithm performs scheduling and module allocation using the time-overlapping information. Experimental results show that significant improvement can be achieved both in speed and in area.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.12
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• pp.58-66
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• 2001

Input queueing is useful for high bandwidth switches and routers because of lower complexity and fewer circuits than output queueing. The input queueing switch, however, suffers HOL-Blocking, which limits the throughput to 58%. To get around this low throughput, many input queueing switches have centralized scheduler, which centralized scheduler restrict the design of the switch architecture. To overcome this problem, we propose a simple scheduler called PRR(Pipelined Round Robin), which is intrinsically distributed and presents to show the effectiveness of the proposed scheduling.

• The Transactions of the Korea Information Processing Society
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• v.5 no.5
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• pp.1172-1184
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• 1998

ILP(Instruction Level Parallelism) processors use code reordering algorithms to expose parallelism in a given sequential program. When applied to a loop, this algorithm produces a software-pipelined loop. In a software-pipelined loop, each iteration contains a sequence of parallel instructions that are composed of data-independent instructions collected across from several iterations. For vector loops, however the software pipelining technique can not expose the maximum parallelism because it schedules the program based only on data-dependencies. This paper proposes to schedule differently for vector loops. We develop an algorithm to detect vector loops at object code level and suggest a new vector scheduling algorithm for them. Our vector scheduling improves the performance because it can schedule not only based on data-dependencies but on loop structure or iteration conditions at the object code level. We compare the resulting schedules with those by software-pipelining techniques in the aspect of performance.