• ETRI Journal
• /
• v.27 no.5
• /
• pp.533-538
• /
• 2005

We developed a pipelined scheduling technique of functional hardware and software modules for platform-based system-on-a-chip (SoC) designs. It is based on a modified list scheduling algorithm. We used the pipelined scheduling technique for a performance analysis of an MPEG4 video encoder application. Then, we applied it for architecture exploration to achieve a better performance. In our experiments, the modified SoC platform with 6 pipelines for the 32-bit dual layer architecture shows a 118% improvement in performance compared to the given basic SoC platform with 4 pipelines for the 16-bit single-layer architecture.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.29A no.4
• /
• pp.74-82
• /
• 1992

This paper deals with the scheduling problems, which are the most important subtask in High-level Synthesis. ILP(integer linear programming) formulations are used as a scheduling problem approach.For practical application to digital system design, we have concentrated our attentions on pipelined datapath scheduling. For experiment results, we choose the 5-th order digital wave filter as a benchmark and do the schedule. Finally, we can obtain better and near-optimal scheduling results.

• Proceedings of the IEEK Conference
• /
• 2002.07b
• /
• pp.1276-1279
• /
• 2002

In order to satisfy the requirement for various applications in an electronic device, many dynamically reconfigurable systems such as FPGAs have been used recently. This paper presents a pipelined scheduling for dynamically reconfigurable systems based on FPGAs. For reconfigurable systems conventional schedulings have reduced processing time by minimizing the number of reconfigurations. However, they are not effective enough for applications including many iterative processes such as digital signal processing. Our approach has been able to increase throughput of iterative applications on dynamically reconfigurable systems by using pipelined scheduling.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.30A no.6
• /
• pp.49-57
• /
• 1993

In the paper, we describe the design of a pipelined datapath synthesis system for DSP applications. Taking SFG (Signal Flow Graph) in schematic as inputs, the system generates pipelined datapaths automatically through scheduling and module allocation processes. For efficient hardware synthesis, scheduling and module allocation algorithms are proposed. The proposed scheduling algorithm is of iterative/constructive nature, where the measure of equi-distribution of operations to partitions is adopted as the objective function. Module allocation is performed to reduce the interconnection cost from the initial allocation. In the experiment, we compare the results with those of other systems and show the effectiveness of the proposed algorithms.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2008.05a
• /
• pp.225-228
• /
• 2008

In this paper, we presented our implementation of a counter mode AES based on Virtex4 FPGA. Our design exploits three advanced features: composite field arithmetic SubByte, efficient MixColumn transformation, and On-the-Fly Key-Scheduling for fully pipelined architecture. By pipelining the composite field implementation of the S-box, the area cost is reduced to average 17 percent. By designing the On-the-Fly key scheduling, we implemented an efficient key-expander module which is specialized for a pipelined architecture.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.25 no.7
• /
• pp.746-758
• /
• 1988

This paper proposes a code scheduling algorithm which gives a software solution to the pipeline interlock. This algorithm provides a heuristic solution by recordering the instructions, instead of using hardware interlock mechanism when pipeline interlock prevents the execution of a machine instruction in a pipelined architecture. Program code size and overall execution time can be reduced due to the increased flexibility in the selection of instructions, which is possible from the alleviated ordering restriction on the use of conflict resources.

• The Transactions of the Korean Institute of Electrical Engineers D
• /
• v.52 no.6
• /
• pp.365-371
• /
• 2003

Input queued switch is useful for high bandwidth switches and routers because of lower complexity and fewer circuits than output queued. The input queued switch, however, suffers the HOL-Blocking, which limits its throughput to 58%. To overcome HOL-Blocking problem, many input-queued switch controlled by a scheduling algorithm. Most scheduling algorithms are implemented based on a centralized scheduler which restrict the design of the switch architecture. In this paper, we propose a simple scheduler called Pipelined Round Robin (PRR) which is intrinsically distributed by each input port. We presents to show the effectiveness of the proposed scheduler.

• The KIPS Transactions:PartA
• /
• v.9A no.3
• /
• pp.379-386
• /
• 2002

This paper presents a scheduling approach for synthesizing pipelined datapaths under resource constraints. Our approach builds up a schedule based on gradual mobility reduction in contrast to other algorithms of previous researches, where an operation being scheduled is selected by using a priority function. The proposed method consists of a scheduling algorithm and a decision algorithm for detecting any violation against resource constraints. Our approach evaluates whether or not a scheduling solution can exist in case an operation temporarily is assigned to the earliest or latest control step among the assignable steps for the operation. If a solution cannot be found, it is impossible to assign the operation to that step due to a violation against resource constraints, and so we can eliminate that control step. This process is iterated until a reduction of mobility for all operations can not be obtained. Experiments on benchmarks show that this approach gains a considerable improvement over those by previous approaches.

• The Transactions of the Korea Information Processing Society
• /
• v.5 no.11
• /
• pp.2973-2979
• /
• 1998

As this paper is a scheduling algorithm for the synthesis of a pipelined datapath under resource constraints in high level synthesis, the proposed heuristic algorithm uses a priority function based on the collision count of resourecs. In order to schedule the pipelined datapath under resource constraints, we define the collision count and the priority function based on the collision count, a number of resource, and the mobility of operations to resolve a resource collision. The proposed algorithm supports chaining, multicycling, and structural pipelining to design the realistic hardware. The evaluation of the Performance is compared with other systems using the results of the synthesis for a 16point FIR filter and a 5th order elliptic wave filter, where in most cases, the optimal solution is obtained.

• Proceedings of the IEEK Conference
• /
• 2008.06a
• /
• pp.409-410
• /
• 2008

This paper presents nonlinear and parallel design for synchronous pipelining in IP-based H.264 decoder implementation. Since H.264 decoder includes the dataflow of feedback loop, the data dependency requires one NOP stage per pipelining latency to drop the throughput into 1/2. Further, it is found that, in execution time, the stage scheduled for MC is more occupied than that for CAVLD/ITQ/DF. The less efficient stage would be improved by nonlinear scheduling, while the fully-utilized stage could be accelerated by parallel scheduling of IP. The optimization yields 3 nonlinear {CAVLD&ITQ}|3 parallel (MC/IP&Rec.)| 3 nonlinear {DF} pipelined architecture for IP-based H.264 decoder. In experiments, the nonlinear and parallel pipelined H.264 decoder, including existing IPs, could deal with full HD video at 41.86MHz, in real time processing.