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http://dx.doi.org/10.3745/KIPSTA.2002.9A.3.379

A Scheduling Approach using Gradual Mobility Reduction for Synthesizing Pipelined Datapaths  

Yoo, Hee-Jin (Suncheon College)
Oh, Ju-Young (Kyungin Womens College)
Lee, Jun-Yong (Dept. of Computer Engineering,Hongik University)
Park, Do-Soon (Dept. of Computer Engineering,Hongik University)
Publication Information
The KIPS Transactions:PartA / v.9A, no.3, 2002 , pp. 379-386 More about this Journal
Abstract
This paper presents a scheduling approach for synthesizing pipelined datapaths under resource constraints. Our approach builds up a schedule based on gradual mobility reduction in contrast to other algorithms of previous researches, where an operation being scheduled is selected by using a priority function. The proposed method consists of a scheduling algorithm and a decision algorithm for detecting any violation against resource constraints. Our approach evaluates whether or not a scheduling solution can exist in case an operation temporarily is assigned to the earliest or latest control step among the assignable steps for the operation. If a solution cannot be found, it is impossible to assign the operation to that step due to a violation against resource constraints, and so we can eliminate that control step. This process is iterated until a reduction of mobility for all operations can not be obtained. Experiments on benchmarks show that this approach gains a considerable improvement over those by previous approaches.
Keywords
high level synthesis; scheduling; Pipelined datapaths;
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  • Reference
1 D. D. Gajski, N. Dutt, A. Wu, and S. Lin, 'High-Level Synthesis : Introduction to Chip and System Design,' Kluwer Academic Publishers, Boston, 1992
2 N. Park, and A. C. Parker, 'Shewa : A software package for synthesis of pipelines from behavioral specification,' IEEE Trans. Computer-Aided Design, Vol.7, pp.356-370, March, 1988   DOI   ScienceOn
3 P. G. Paulin and J. P. Knight, 'Force-directed scheduling for behavioral synthesis of ASI's,' IEEE Trans. Computer-Aided Design, Vol.8, pp.661-679, March, 1989   DOI   ScienceOn
4 W. F. J. Verhaegh, P. E. R. Lippens, E. H. L. Aarts, J. H. M. Korst, A. van der Werf and J. L. van Merbergen, 'Efficiency Improvements for Force-Directed Scheduling,' Computer-Aided Design, pp.286-291, 1992   DOI
5 Y. H. Choi, 'Synthesis of pipelined datapaths,' Proc.Int. Conf. Computer-Aided Design, , pp.36-40, Jan., 1992   DOI   ScienceOn
6 T. F. Lee, A. C. Wu, D. D. Gajski and Y. L. Lin, 'An effective methodology for functional pipelining,' in Proc. Int. Conf. Computer-Aided Design, pp.230-233, 1992   DOI
7 K. S. Hwang, A. E. Casavant, C. T. Chang and A. d'Abreu Manuel, 'Scheduling and Hardware Sharing in Pipelined Data Path,' in Proc. Int. Conf. Computer-Aided Design, pp.24-27, 1989   DOI
8 C. T. Hwang, Y. C. Hsu and Y. L. Lin, 'PLS : A scheduler for pipeline synthesis,' IEEE Trans. on CAD/ICSA, Vol.12, No.9, pp.1279-1286, Sep., 1993   DOI   ScienceOn
9 J. Lee, Y. Hsu, and Y. Lin, 'A New Integer Linear Programming Formulation for the Scheduling Problem in Data-Path Synthesis,' in Proc. Int. Conf. Computer-Aided Design, pp.20-23, 1989   DOI
10 C. T. Hwang, Y. C. Hsu and Y. L. Lin, 'Scheduling for functional Pipelining and Loop Winding,' in Proc.28th Design Automation Conf., pp.764-769, 1991   DOI
11 G. D. Micheli, 'Synthesis and Optimization of Digital Circuits,' Mcgraw-Hill, 1994
12 Y. C. Hsu and Y. L. Jeang, 'Pipeline Scheduling Techniques in High-Level Synthesis,' in Proc. Int. Conf. Computer-Aided Design, pp.396-403, 1993   DOI