• ETRI Journal
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• 제27권5호
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• pp.533-538
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• 2005

We developed a pipelined scheduling technique of functional hardware and software modules for platform-based system-on-a-chip (SoC) designs. It is based on a modified list scheduling algorithm. We used the pipelined scheduling technique for a performance analysis of an MPEG4 video encoder application. Then, we applied it for architecture exploration to achieve a better performance. In our experiments, the modified SoC platform with 6 pipelines for the 32-bit dual layer architecture shows a 118% improvement in performance compared to the given basic SoC platform with 4 pipelines for the 16-bit single-layer architecture.

• 전자공학회논문지A
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• 제29A권4호
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• pp.74-82
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• 1992

This paper deals with the scheduling problems, which are the most important subtask in High-level Synthesis. ILP(integer linear programming) formulations are used as a scheduling problem approach.For practical application to digital system design, we have concentrated our attentions on pipelined datapath scheduling. For experiment results, we choose the 5-th order digital wave filter as a benchmark and do the schedule. Finally, we can obtain better and near-optimal scheduling results.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -2
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• pp.1276-1279
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• 2002

In order to satisfy the requirement for various applications in an electronic device, many dynamically reconfigurable systems such as FPGAs have been used recently. This paper presents a pipelined scheduling for dynamically reconfigurable systems based on FPGAs. For reconfigurable systems conventional schedulings have reduced processing time by minimizing the number of reconfigurations. However, they are not effective enough for applications including many iterative processes such as digital signal processing. Our approach has been able to increase throughput of iterative applications on dynamically reconfigurable systems by using pipelined scheduling.

• 전자공학회논문지A
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• 제30A권6호
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• pp.49-57
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• 1993

In the paper, we describe the design of a pipelined datapath synthesis system for DSP applications. Taking SFG (Signal Flow Graph) in schematic as inputs, the system generates pipelined datapaths automatically through scheduling and module allocation processes. For efficient hardware synthesis, scheduling and module allocation algorithms are proposed. The proposed scheduling algorithm is of iterative/constructive nature, where the measure of equi-distribution of operations to partitions is adopted as the objective function. Module allocation is performed to reduce the interconnection cost from the initial allocation. In the experiment, we compare the results with those of other systems and show the effectiveness of the proposed algorithms.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2008년도 춘계종합학술대회 A
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• pp.225-228
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• 2008

In this paper, we presented our implementation of a counter mode AES based on Virtex4 FPGA. Our design exploits three advanced features: composite field arithmetic SubByte, efficient MixColumn transformation, and On-the-Fly Key-Scheduling for fully pipelined architecture. By pipelining the composite field implementation of the S-box, the area cost is reduced to average 17 percent. By designing the On-the-Fly key scheduling, we implemented an efficient key-expander module which is specialized for a pipelined architecture.

• 대한전자공학회논문지
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• 제25권7호
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• pp.746-758
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• 1988

This paper proposes a code scheduling algorithm which gives a software solution to the pipeline interlock. This algorithm provides a heuristic solution by recordering the instructions, instead of using hardware interlock mechanism when pipeline interlock prevents the execution of a machine instruction in a pipelined architecture. Program code size and overall execution time can be reduced due to the increased flexibility in the selection of instructions, which is possible from the alleviated ordering restriction on the use of conflict resources.

• 대한전기학회논문지:시스템및제어부문D
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• 제52권6호
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• pp.365-371
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• 2003

Input queued switch is useful for high bandwidth switches and routers because of lower complexity and fewer circuits than output queued. The input queued switch, however, suffers the HOL-Blocking, which limits its throughput to 58%. To overcome HOL-Blocking problem, many input-queued switch controlled by a scheduling algorithm. Most scheduling algorithms are implemented based on a centralized scheduler which restrict the design of the switch architecture. In this paper, we propose a simple scheduler called Pipelined Round Robin (PRR) which is intrinsically distributed by each input port. We presents to show the effectiveness of the proposed scheduler.

• 정보처리학회논문지A
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• 제9A권3호
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• pp.379-386
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• 2002

본 논문은 자원제약 조건에서 파이프라인 데이터패스 합성을 위한 스케줄링 방법이며, 우선순위 함수를 사용하여 스케줄할 연산을 선택하는 방법들과는 달리 연산들의 배정가능범위를 점진적으로 축소하여 스케줄한다. 제안방법은 스케줄링 알고리즘과 자원제약 위반을 검출하는 판단알고리즘으로 구성되며, 연산의 배정 가능한 제어단계의 처음 또는 마지막 단계에 임시로 연산을 배정하여 스케줄링 해가 존재하는지를 평가한다. 만약 해를 발견할 수 없다면 이는 자원제약 위반에 의해 연산을 그 제어단계에 배정하는 것이 불가능함을 의미하기 때문에 그 제어단계를 제거하며, 모든 연산에 대하여 배정가능범위 축소가 없을 때까지 이 과정을 반복한다. 벤치마크에 대한 실험결과는 다른 방법들과 비교해서 개선된 스케줄링 결과를 보인다.

• 한국정보처리학회논문지
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• 제5권11호
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• pp.2973-2979
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• 1998

본 논문은 상위 수준 합성식의 자원 제약 조건하에서 파이프라인 데이타패스 합성을 위한 스케쥴링 알고리즘으로, 제안된 휴리스틱 알고리즘은 자원의 충돌수에 근거한 우선순위 함수를 사용한다. 자원 제약하에서 파이프라인 데이타패스 합성수를 정의하여 스케쥴링 한다. 제안 알고리즘은 실질적인 하드웨어 설계를 위해 체이닝, 멀티사이클링, 구조적 파이프라인이 지원되도록 한다. 제안 알고리즘에 의한 16 포인트 FIR 필터와 5차 엘립틱 웨이브 필터 합성 결과에 의해 다른 시스템들과의 성능을 비교하였으며, 대부분의 경우에 최적의 해를 찾을 수 있었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.409-410
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• 2008

This paper presents nonlinear and parallel design for synchronous pipelining in IP-based H.264 decoder implementation. Since H.264 decoder includes the dataflow of feedback loop, the data dependency requires one NOP stage per pipelining latency to drop the throughput into 1/2. Further, it is found that, in execution time, the stage scheduled for MC is more occupied than that for CAVLD/ITQ/DF. The less efficient stage would be improved by nonlinear scheduling, while the fully-utilized stage could be accelerated by parallel scheduling of IP. The optimization yields 3 nonlinear {CAVLD&ITQ}|3 parallel (MC/IP&Rec.)| 3 nonlinear {DF} pipelined architecture for IP-based H.264 decoder. In experiments, the nonlinear and parallel pipelined H.264 decoder, including existing IPs, could deal with full HD video at 41.86MHz, in real time processing.