• ETRI Journal
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• 제34권4호
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• pp.518-526
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• 2012

This paper proposes LC voltage-controlled oscillator (VCO) phase-locked loop (PLL) and ring-VCO PLL topologies with low-phase noise. Differential control loops are used for the PLL locking through a symmetrical transformer-resonator or bilaterally controlled varactor pair. A differential compensation mechanism suppresses out-band spurious tones. The prototypes of the proposed PLL are implemented in a CMOS 65-nm or 45-nm process. The measured results of the LC-VCO PLL show operation frequencies of 3.5 GHz to 5.6 GHz, a phase noise of -118 dBc/Hz at a 1 MHz offset, and a spur rejection of 66 dBc, while dissipating 3.2 mA at a 1 V supply. The ring-VCO PLL shows a phase noise of -95 dBc/Hz at a 1 MHz offset, operation frequencies of 1.2 GHz to 2.04 GHz, and a spur rejection of 59 dBc, while dissipating 5.4 mA at a 1.1 V supply.

• Journal of Power Electronics
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• 제12권4호
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• pp.604-614
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• 2012

This paper presents a comparative study of position sensorless control schemes based on back-electromotive force (back-EMF) estimation in permanent magnet synchronous motors (PMSM). The characteristics of the estimated back-EMF signals are analyzed using various mathematical models of a PMSM. The transfer functions of the estimators, based on the extended EMF model in the rotor reference frame, are derived to show their similarity. They are then used for the analysis of the effects of both the motor parameter variations and the voltage errors due to inverter nonlinearity on the accuracy of the back-EMF estimation. The differences between a phase-locked-loop (PLL) type estimator and a Luenberger observer type estimator, generally used for extracting rotor speed and position information from estimated back-EMF signals, are also examined. An experimental study with a 250-W interior-permanent-magnet machine has been performed to validate the analyses.

• 전기학회논문지
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• 제65권5호
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• pp.794-803
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• 2016

This paper propose a sensorless control system of IPMSM with a adaptive back-EMF estimator and improved instantaneous reactive power compensator. A saliency-based back-EMF is estimated by using the adaptive algorithm. The estimated back-EMF is inputted to the phase locked loop(PLL) and the improved instantaneous reactive power(IRP) compensator for estimating the position/speed of the rotor and compensating the error components between the estimated and the actual position, respectively. The stability of the proposed system is achieved through Popov's hyper stability criteria. The validity of proposed algorithm is verified by the simulations and experiments.

• 전자공학회논문지SC
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• 제44권1호
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• pp.74-84
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• 2007

본 논문에서는 기존의 DLL 지연 시간 잠금 범위를 확장하기 위해 새로운 이중 루프 DLL을 제안하였다. 제안한 DLL은 Coarse_loop와 Fine_loop를 포함하고 있으며, 와부 클럭과 2개의 내부 클럭 사이의 초기 시간차를 비교하여 하나의 루프를 선택하여 동작하게 된다. 2개의 내부 클럭은 VCDL의 중간 출력 클럭과 최종 출력 클럭이며 두 클럭의 위상차는 $180^{\circ}$이다. 제안한 DLL은 일반적인 잠금 범위 밖에 있을 경우 Coarse_loop를 선택하여 잠금 범위 안으로 이전 시킨 후 Fine_loop에 의하여 잠금 상태가 일어난다. 따라서 제안한 DLL은 harmonic lock이 일어나지 않는 한 항상 안정적으로 잠금 과정이 일어날 수 있게 된다. 제안한 DLL이 사용하는 VCDL은 두 개의 제어 전압을 받아 지연 시간을 조절함으로 일반적인 다 적층 currentstarved 형태의 인버터 대신에 TG 트랜지스터를 이용하는 인버터를 사용하여 지연 셀을 구성하였다. 새로운 VCDL은 종래의 VCDL에 비하여 지연시간 범위가 더욱 확장되었으며, 따라서 제안한 DLL의 잠금 범위는 기존의 DLL의 잠금 범위보다 2배 이상 확장되었다. 본 논문에서 제안한 DLL 회로는 0.18um, 1.8V TSMC CMOS 라이브러리를 기본으로 하여 설계, 시뮬레이션 및 검증하였으며 동작 주파수 범위가 100MHz${\sim}$1GHz이다. 또한, 1GHz에서 제안한 DLL의 잠금 상태에서의 최대 위상 오차는 11.2ps로 높은 해상도를 가졌으며, 이때 소비 전력은 11.5mW로 측정되었다.

• Journal of Electrical Engineering and Technology
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• 제5권4호
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• pp.606-613
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• 2010

This paper proposes a novel current-based maximum power point tracking (CMPPT) method for a single-phase photovoltaic power conditioning system (PV PCS) by using a modified incremental conductance method. The CMPPT method simplifies the entire control structure of the power conditioning system and uses an inherent current source characteristic of solar cell arrays. Therefore, it exhibits robust and fast response under a rapidly changing environmental condition. Digital phase locked loop technique using an all-pass filter is also introduced to detect the phase of grid voltage, as well as the peak voltage. Controllers of dc/dc boost converter, dc-link voltage, and dc/ac inverter are designed for coordinated operation. Furthermore, a current control using a pseudo synchronous d-q transformation is employed for grid current control with unity power factor. A 3 kW prototype PV PCS is built, and its experimental results are given to verify the effectiveness of the proposed control schemes.

• Journal of Power Electronics
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• 제14권3호
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• pp.598-607
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• 2014

This paper proposes a frequency-locked loop (FLL) scheme for a single-phase grid-connected converter. A second-order generalized integrator (SOGI) based on fuzzy logic (FL) is applied to this converter to achieve precise phase angle detection. The use of this method enables the compensation of the nonlinear characteristic of the frequency error, which is defined in the SOGI scheme as the variation of the central frequency through the self-tuning gain. With the proposed scheme, the performance of the SOGI-FLL is further improved at the grid disturbances, which results in the stable operation of the grid converter under grid voltage sags or frequency variation. The PSIM simulation and experimental results are shown to verify the effectiveness of the proposed method.

• 한국태양에너지학회 논문집
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• 제29권5호
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• pp.65-72
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• 2009

The new method is proposed to improve high speed detection of grid voltage phase and magnitude during a voltage dip due to a grid faults. Usually, A LPF(Low Pass Filter) is used in the feedback loop of PLL (Phase Locked Loop) system because the measured grid voltage contains harmonic distortions and sensor noises. so, a new design method of the loop gain of the PI -type controller in the PLL system is proposed with the consideration of the dynamics of the LPF. As a result, a better transient response can be obtained with the proposed design method. The LPF frequency and PI controller gain are designed in coordination according to the steady state and dynamic performance requirement. This paper shows the feasibility and the usefulness of the proposed methods through the computer simulation and the lab-scale experiments.

• 전기학회논문지
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• 제57권10호
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• pp.1796-1801
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• 2008

In this paper, a new current based maximum power point tracking (CMPPT) method is proposed for a single phase photovoltaic power conditioning system and the current based MPPT modifies incremental conductance method. The current based MPPT method makes the entire control structure of the power conditioning system simple and uses an inherent current source characteristic of solar cell array. In addition, digital phase locked loop using an all pass filter is introduced to detect phase of grid voltage as well as peak voltage. Controllers about dc/dc boost converter, dc-link voltage, dc/ac inverter is designed for a coordinated operation. Furthermore, PI current control using a pseudo synchronous d-q transformation is employed for grid current control with unity power factor. 3kW prototype photovoltaic power conditioning system is built and its experimental results are given to verify the effectiveness of the proposed control schemes.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 추계학술대회 논문집 학회본부
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• pp.456-458
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• 1997

The phase-lock technique is applied to a three-phase semi-bridge type battery charger system. Using an inner fast dynamic loop, the phase-locked voltage control (PLVC) technique of three-phase semi-bridge converter is proposed to give a frequency synchronism and to reduce the subharmonics due to the unbalance of transformer or power line. To protect the power devices, the two stage soft-start, function with softly locking the phase and softly increasing the current is presented. As limiting the reference voltage of the inner voltage control loop, muti-lock phenomena are removed on the PLVC loop. A current limit function is also proposed to limit the current of battery and converter. The proposed controller is confirmed through experiment results.

• 전력전자학회논문지
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• 제14권2호
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• pp.96-104
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• 2009

본 논문에서는 단상 전원의 위상 및 주파수 검출을 위해 전차원 상태관측기를 이용한 가상 2상 방식의 단상 위상고정루프(PLL: Phase Locked Loop) 제어기를 제안한다. 기존의 방식은 전원단에 주입된 저차 고조파를 완벽하게 제거하지 못하여 전체 PLL 시스템에 영향을 주게 된다. 제안된 알고리즘은 전차원 상태관측기를 사용하여 기본파와 고조파를 분리하고 고조파 성분을 효과적으로 제거 및 검출하여 기본파 성분만을 발생한다. 그리고 가상 발생신호 및 기존 입력신호를 함께 제어함으로써 기존방식보다 정상상태 오차를 감소시킬 수 있다. 모의실험결과 및 실제실험결과를 통하여 설계한 제어기에 의해 발생된 주파수가 실제값에 수렴하였으며 정상상태 추정 특성이 향상됨을 검증하였다. 또한 고조파 성분이 효과적으로 제거되고 기본파 성분만을 출력하는 것을 확인하였다.