• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2007.06a
• /
• pp.156-157
• /
• 2007

For tens of years many advantages of Phase-Change Random Access Memory(PRAM) were introduced. Although the performance improved gradually, there are some portions which must be improved. So, we studied new constitution of $Ge_1Se_1Te_2$ chalcogenide material to improve phase transition characteristic. Actually, the performance properties have been improved surprisingly. However, crystallization time was as long as ever for amorphization time. We conducted this experiment in order to solve that problem by doping-Sb.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.11 no.2
• /
• pp.107-116
• /
• 2016

Density of Phase-Change Memory (PCM) devices has been doubled through the employment of multi-level cell (MLC) technology. However, this doubled-capacity comes in the expense of severe performance degradation, as compared to the conventional single-level cell (SLC) PCM. This negative effect on the performance of the MLC PCM detracts from the potential benefits of the MLC PCM. This paper introduces an efficient way of minimizing the performance degradation while maximizing the capacity benefits of the MLC PCM. To this end, we propose a location-aware hybrid management of SLC and MLC in compressed PCM main memory systems. Our trace-driven simulations using real application workloads demonstrate that the proposed technique enhances the performance and energy consumption by 45.1% and 46.5%, respectively, on the average, over the conventional technique that only uses a MLC PCM.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.3
• /
• pp.330-338
• /
• 2016

Phase change memory (PCM) has been studied as an emerging memory technology for last-level cache (LLC) due to its extremely low leakage. However, it consumes high levels of energy in updating cells and its write endurance is limited. To relieve the write pressure of LLC, we propose a delta value indicator (DVI) by employing a small cache which stores the difference between the value currently stored and the value newly loaded. Since the write energy consumption of the small cache is less than the LLC, the energy consumption is reduced by access to the small cache instead of the LLC. In addition, the lifetime of the LLC is further extended because the number of write accesses to the LLC is decreased. To this end, a delta value indicator and controlling circuits are inserted into the LLC. The simulation results show a 26.8% saving of dynamic energy consumption and a 31.7% lifetime extension compared to a state-of-the-art scheme for PCM.

• Journal of Advanced Marine Engineering and Technology
• /
• v.32 no.1
• /
• pp.162-168
• /
• 2008

In this paper, we analyzed the heat transfer phenomenon and the reset current variation of PRAM device with thickness of phase change material using the 3-D finite element analysis tool. From the simulation, Joule's heat was generated at the contact surface of phase change material and bottom electrode of PRAM. As the thickness of phase change material was decreased, the reset current was highly increased. In case thickness of phase change material thin film was $200\;{\AA}$, heat increased through top electrode and reset current caused by phase transition highly increased. And as thermal conductivity of top electrode decreased, temperature of unit memory cell was increased.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2005.07a
• /
• pp.15-16
• /
• 2005

Chalcogenide phase change memory has high performance to be next generation memory, because it is a nonvolatile memory processing high programming speed, low programming voltage, high sensing margin, low consumption and long cycle duration. We have developed a new material of PRAM with $Ge_1Se_1Te_2$. This material has been propose to solve the high energy consumption and high programming current. We have investigated the phase transition behaviors in function of various process factor including contact size, cell size, and annealing time. As a result, we have observed that programming voltage and writing current of $Ge_1Se_1Te_2$ are more improved than $Ge_2Sb_2Te_5$ material.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.27 no.2
• /
• pp.76-80
• /
• 2014

Dual-gate PCRAM which unify capacitor-less DRAM and NVM using a PCM instead of a typical SONOS flash memory is proposed as 1 transistor. $VO_2$ changes its phase between insulator and metal states by temperature and field. The front-gate and back-gate control NVM and DRAM, respectively. The feasibility of URAM is investigated through simulation using c-interpreter and finite element analysis. Threshold voltage of NVM is 0.5 V that is based on measured results from previous fabricated 1TPCM with $VO_2$. Current sensing margin of DRAM is 3 ${\mu}A$. PCM does not interfere with DRAM in the memory characteristics unlike SONOS NVM. This novel unified dual-gate PCRAM reported in this work has 1 transistor, a low RESET/SET voltage, a fast write/erase time and a small cell so that it could be suitable for future production of URAM.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.10 no.6
• /
• pp.391-397
• /
• 2015

Nonvolatile memories in memory hierarchy have been investigated to reduce its energy consumption because nonvolatile memories consume zero leakage power in memory cells. One of the difficulties is, however, that the endurance of most nonvolatile memory technologies is much shorter than the conventional SRAM and DRAM technology. This has limited its usage to only the low levels of a memory hierarchy, e.g., disks, that is far from the CPU. In this paper, we study the use of a new type of nonvolatile memories - the Phase Change Memory (PCM) with a DRAM buffer system as the main memory. Our design reduced the total energy of a DRAM main memory of the same capacity by 80%. These results indicate that it is feasible to use PCM technology in place of DRAM in the main memory for better energy efficiency.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.19 no.10
• /
• pp.918-922
• /
• 2006

Chalcogenide Phase change memory has the high performance necessary for next-generation memory, because it is a nonvolatile memory with high programming speed, low programming voltage, high sensing margin, low power consumption and long cycle duration. To minimize the power consumption and the program voltage, the new composition material which shows the better phase-change properties than conventional $Ge_2Sb_2Te_5$ device has to be needed by accurate material engineering. In the present work, we investigate the basic thermal and the electrical properties due to phase-change compared with chalcogenide-based new composition $Ge_1Se_1Te_2$ material thin film and convetional $Ge_2Sb_2Te_5$ PRAM thin film. The fabricated new composition $Ge_1Se_1Te_2$ thin film exhibited a successful switching between an amorphous and a crystalline phase by applying a 950 ns -6.2 V set pulse and a 90 ns -8.2 V reset pulse. It is expected that the new composition $Ge_1Se_1Te_2$ material thin film device will be possible to applicable to overcome the Set/Reset problem for the nonvolatile memory device element of PRAM instead of conventional $Ge_2Sb_2Te_5$ device.

• International Journal of Internet, Broadcasting and Communication
• /
• v.14 no.1
• /
• pp.188-193
• /
• 2022

The energy efficiency of memory systems is an important task in designing future computer systems as memory capacity continues to increase to accommodate the growing big data. In this article, we present an energy-efficient last-level cache management policy for future mobile systems. The proposed policy makes use of low-power PCM (phase-change memory) as the main memory medium, and reduces the amount of data written to PCM, thereby saving memory energy consumptions. To do so, the policy keeps track of the modified cache lines within each cache block, and replaces the last-level cache block that incurs the smallest PCM writing upon cache replacement requests. Also, the policy considers the access bit of cache blocks along with the cache line modifications in order not to degrade the cache hit ratio. Simulation experiments using SPEC benchmarks show that the proposed policy reduces the power consumption of PCM memory by 22.7% on average without degrading performances.

• Journal of Advanced Marine Engineering and Technology
• /
• v.29 no.6
• /
• pp.707-712
• /
• 2005

PRAM (Phase change random access memory) is one of the most promising candidates for next generation Non-volatile Memories. The Phase change materials have been researched in the field of optical data storage media. Among the phase change materials. $Ge_2Sb_2Te_5$ is very well known for its high optical contrast in the state of amorphous and crystalline. However the characteristics required in solid state memory are quite different from optical ones. In this study. the structural Properties of GeSbTe thin films with composition were investigated for PRAM. The 100-nm thick $Ge_2Sb_2Te_5$ and $Sb_2Te_3$ films were deposited on $SiO_2/Si$ substrates by RF sputtering system. In order to characterize the crystal structure and morphology of these films. x-ray diffraction (XRD). atomic force microscopy (AFM), differential scanning calorimetry (DSC) and 4-point measurement analysis were performed. XRD and DSC analysis result of GST thin films indicated that the crystallization of $Se_2Sb_2Te_5$ films start at about $180^{\circ}C$ and $Sb_2Te_3$ films Start at about $125^{\circ}C$.