• Journal of Power Electronics
• /
• v.18 no.3
• /
• pp.802-816
• /
• 2018

A digital direct phase-shift control (DDPSC) method based on the phase-shifted full-bridge LLC (PSFB-LLC) converter is presented. This work combines DDPSC with the conventional linear control to obtain a hybrid control strategy that has the advantages of linear control and DDPSC control. The strategy is easy to realize and has good dynamic responses. The PSFB-LLC circuit structure is simple and works in the fixed frequency mode, which is beneficial to magnetic component design; it can realize the ZVS of the switch and the ZCS of the rectifier diode in a wide load range. In this work, the PSFB-LLC converter resonator is analyzed in detail, and the concrete realization scheme of the hybrid control strategy is provided by analyzing the state-plane trajectory and the time-domain model. Finally, a 3 kW prototype is developed, and the feasibility and effectiveness of the DDPSC controller and the hybrid strategy are verified by experimental results.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.15 no.5
• /
• pp.13-18
• /
• 1978

A delay switching PLL (DSPLL) is proposed for improvement of the frequency acquisition Performance (pull-in range) while keeping a narrow bandwidth LPF. It has, between the phase detector and the LPF, just a simple RC delay circuit, a switch and another phase detector controlling the switching time. For the common second order PLL, the pull-in capability of the DSPLL is analyzed approximately, without considering additive white noise effect, and verified experimentally. It is shown that the delay switching extends the pull-in range significantly, as much as a half of lock-range. At the phase tracking mode, the delay switching does not function, to make the DSPLL be a normal PLL.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.14 no.6
• /
• pp.479-486
• /
• 2021

In this paper, an ultra small phase locked loop (PLL) with a single capacitor loop filter has been proposed by adding a signal sensing circuit (SSC). In order to extremely reduce the size of the PLL, the passive element loop filter, which occupies the largest area, is designed with a very small single capacitor (2pF). The proposed PLL is designed to operate stably by the output of the internal negative feedback loop including the SSC acting as a negative feedback to the output of the single capacitor loop filter of the external negative feedback loop. The SSC that detects the PLL output signal change reduces the excess phase shift of the PLL output frequency by adjusting the capacitance charge of the loop filter. Although the proposed structure has a capacitor that is 1/78 smaller than that of the existing structure, the jitter size differs by about 10%. The PLL is designed using a 1.8V 180nm CMOS process and the Spice simulation results show that it works stably.

• Proceedings of the KIPE Conference
• /
• 2001.07a
• /
• pp.348-351
• /
• 2001

In this paper, voltage-fed high frequency resonant inverter of instantaneous current phaser control method used to DC voltage source separated is proposed. In the output control method, a novel circuit type of phase shift driving signal method with CVCF illustrated, also the operation principle of the proposed circuit is described in detail and its characteristics are presented as to normalized parameters. According to the each mode, in order to the circuit analysis and characteristic evaluation of the state equation are derives and present used to normalized parameter. In the future, this proposed inverter show that it can be practically used as power source system for the lighting equipment of discharge lamp, DC-DC converter etc.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.13 no.6
• /
• pp.1177-1182
• /
• 2018

We designed a 500W zero voltage switching DC / DC converter operating at 100Mhz with phase shift topology using UCC3895 driver. The dead time of the UCC3895 driver is designed so that the leading and lagging leg of the full bridge can be driven separately. So, the dead time can be given between the two legs separately. The dead time, which is an asymmetrical relationship between the two legs, enables the implementation of zero voltage switching. This paper proposed a negative feedback circuit design method for stable output voltage. The maximum efficiency of the prototype was 95.5% at $500{\Omega}$ load.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.12 no.5
• /
• pp.400-408
• /
• 2007

In this paper, development of the 8kW parallel module converter is presented. For a effective configuration of FB-PWM converter, this paper proposes 4-parallel operation of 2 kw-module. FB converter of 2-kW module is controlled by phase shut PWM and in order to achieve ZVZCS, the simple auxiliary circuit is applied in secondary side. In order to achieve ZCS, control logic for auxiliary circuit operation is designed to reset the primary current during free-wheeling period. For output current sharing of 4-modules, the charge control is employed. The charge control logic is designed with phase shift PWM logic. Voltage controller is implemented by using DSP(TMS320LF2406) with A/D conversion data of the output current and voltage of each module. The developed converter is installed in PCU(Power Conditioning Unit) for HSG(High Speed Generator) in a vehicle and health monitoring system is implemented for vehicle operation test. Finally, performance of the developed converter is proved under practical operation of HSG.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.37 no.3
• /
• pp.1-8
• /
• 2000

This paper presents a simulation model of the Quadrature detector to demodulate FSK signal, which is widely used in wireless paging system for its simple hardware implementation and economics of It fabrication. Quadrature detecter has nonlinear phase characteristic for changes linear changes of input signal frequency. So until now Quadrature detector system analysis remained a difficult problem and performance analysis has not been carried out adequately On these backgrounds, this paper presents the FSK signal demodulation process using Quadrature detector and optimal performance derived from digital simulation technique. First, PSN(Phase Shift Network) which is composed of analog RLC tank circuit is transformed into its equivalent digital transfer function using First-order-hold theorem. Though the demodulated outputs of the Quadrature detector for 4FSK are 4-level signals, only 2 comparators are used and it is shown that optimal performance can be obtained by choosing operation parameter Q value and threshold level decision which are proposed herein.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.8 no.5
• /
• pp.452-461
• /
• 1997

In this paper, we present a computer-aided design(CAD) technique for minimizing the phase shift in microstrip PIN diode attenuators due to the junction capacitance in the equivalent circuit model of PIN diode. Microstrip PIN diode attenuators use the characteristics which the reactance of microstrip line changes from inductive to capacitive as the frequency sweeps across the band. Microstrip PIN diode attenuator designed utilizes the quarter-wavelength transmission line terminating with the half-moon radial stub, which is designed for negligible phase shifting effect over the intersted bandwidth. The attenuator has similar phase shift at 0 dB and 10 dB of attenuation within average $1.27^{\circ}$ between 1.2GHz and 1.9GHz. The input and output return losses between 1.4 GHz and 1.9 GHz are less than 10 dB over the attenuation range of 0 dB and 10 dB.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.31 no.3C
• /
• pp.237-244
• /
• 2006

I/Q phase unbalance caused by non-ideal circuit components is inevitable physical phenomenons and leads to performance degradation when we implement a practical coherent M-ary phase shift keying(M-PSK) demodulator. In this paper, we present an exact and general expression involving two-dimensional Gaussian Q-functions for the bit error rate(BER) of uniform M-PSK with I/Q phase unbalance over an additive white Gaussian noise(AWGN) channel. First we derive a BER expression for the k-th bit of 8, 16-PSK signal constellations when Gray code bit mapping is employed. Then, from the derived k-th bit BER expression, we present the exact and general average BER expression for M-PSK with I/Q phase unbalance. This result can readily be applied to numerical evaluation for various cases of practical interest in an I/Q unbalanced M-PSK system, because the one- and two-dimensional Gaussian Q-functions can be easily and directly computed using commonly available mathematical software tools.

• Proceedings of the KIEE Conference
• /
• 2004.04a
• /
• pp.140-142
• /
• 2004

본 논문에서는 UC3879 PWM 제어기를 사용한 풀브릿지 위상천이 컨버터의 출력전압 피드백 신호선의 개방과 과전압이 발생하였을 경우에 컨버터를 안정적으로 유지시키기 위한 보호 회로를 제안하고 있다.