• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6C
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• pp.505-511
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• 2008

The global navigation satellite system (GNSS) is using a direct sequence/spread spectrum (DS/SS) modulation. In order to recover the information data, the DS/SS system first performs a two-step synchronization process: acquisition and tracking. The acquisition process adjusts the phase difference between the received and locally generated acquisition sequences within ${\pm}T_c/2$ or less, where $T_c$ is the chip period. The tracking process performs fine synchronization. In this paper, we focus on the tracking issue. The single delta delay locked loop($\Delta$-DLL) is the optimal tracking scheme for a GNSS in the absence of multipath signals, where $\Delta$ means the spacing between the early and late correlation time offset. In the multipath environments, however, the $\Delta$-DLL suffers from huge estimation bias(denoted by $\beta$) caused by distorted correlation values. Although some modified schemes such as a $\Delta$-DLL with a narrow $\Delta$ and a double delta DLL (${\Delta}^{(2)}$-DLL) were proposed to reduce the estimation bias, they cannot remove the estimation bias completely and need more accurate acquisition process. This paper proposes a novel tracking scheme that can dramatically reduce the estimation bias, using the maximum slope change among the correlation outputs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.7-13
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• 2011

This paper presents a Time-to-Digital Converter which is a key block of an All-Digital Phase Locked Loop. In this work, a Vernier Delay Line is added in a conventional Gated Ring Oscillator, so it could get multi-phases and a high resolution. The Gated Ring Oscillator uses 7 unit delay cell, the Vernier Delay Line is used each delay cell. So proposed Time-to-Digital Converter uses total 21 phases. This Time-to-Digital Converter circuit is designed and laid out in $0.13{\mu}m$ 1P-6M CMOS technology. The proposed Time-to-Digital Converter achieves 26ps resolution, maximum input signal frequency is 100MHz and the digital output of proposed Time-to-Digital Converter are 8-bits. The proposed TDC detect 5ns phase difference between Start and Stop signal. A power consumption is 8.4~12.7mW depending on Enable signal width.

• Journal of the Korean Society of Marine Environment & Safety
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• v.23 no.6
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• pp.739-745
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• 2017

Many studies have been conducted to reduce environmental pollution by ships and reduce fuel consumption. As part of this effort, research on power conversion systems through DC distribution systems that link renewable energy with conventional power grids has been pursued as well. The diode rectifiers currently used include many lower harmonics in the input current of the load and distort supply voltage to lower the power quality of the whole system. This distortion of voltage waveforms causes the malfunctions of generators, load devices and inverter pole switching elements, resulting in a large number of switching losses. In this paper, a controller is presented to improve DC output waveforms, the input Power Factor and the THD of an AFE type PWM rectifier used for PLL. DC output voltage waveforms have been improved, and the input Power Factor can now be matched to the unit power factor. In addition, the THD of the input power supply has been proven by simulation to comply with the requirements of IEEE Std514-2014.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 1991.04a
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• pp.95-98
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• 1991

회전 기기의 이상으로 인하여 발생하는 진동은 축 회전속도의 고주파 성분 (super-harmonic)이나 또는 분수조파 성분(sub-harmonic)으로 나타나는 경 우가 대부분이기 때문에 회전기기의 진동을 주파수 영역에서 해석함에 있어 파워 스펙트럼의 주파수 축을 Hz로 나타내기보다는 축 회전속도의 order로 써 나타내는 것이 매우 유용하다. 스펙트럼을 order로써 나타내기 위해서는 샘플링 시간을 축 회전속도와 동기(synchronization)시켜야 하는데 이 방법으 로는 회전축에 엔코더(encorder)를 부착하여 엔코더에서 발생하는 펄스 신호 를 이용하여 샘플링하는 방법과 order tracking 필터를 이용하는 방법이 있 다. 그러나 전자의 방법은 원하는 회전축마다 엔코더를 부착하여야 하며 경 우에 따라서는 엔코더를 부착하기가 어려운 경우도 있으며, 회전기기의 운전 개시나 종료시처럼 회전속도가 급격히 변화하는 경우에는 낮은 주파수에서 중첩(aliasig)에 의한 오차가 수반될 수도 있다. 후자의 방법은 order tracking 필터 이외에도 여러 부수장비가 필요하며 기준 주파수(즉 회전속 도)가 급격히 변화하는 경우 PLL(phase locked loop)에서 tracking 오차가 발생된다. 최근에 발표된 논문에서 일정한 시간간격으로 샘플링한 데이터들 로부터 신호를 재합성하여 회전축의 속도와 동기가 되도록 재 샘플링함으로 서 스펙트럼의 주파수를 회전속도의 order로써 나타내는 방법을 제시하였다. 그러나 위 논문에서는 신호의 재합성에 필요한 재합성 필터(reconstruction filter)의 설계 방법에 대하여 구체적인 언급이 없이 다만 결과만을 논하였다. 따라서 본 논문에서는 재합성 필터의 설계 방법에 대하여 구체적인 방법을 제시하고 또한 동기화 샘플링의 장점 및 고려 사항에 대하여 고찰하였다. 고려한 능동 소음제어 에 대해 연구하였다. 경량화 추세에 따라 지반이나 케이싱이 경량이거나 유연하여 회전축과 동적으로 연성된 경우 회전축-베어링-지반으로 이루어진 2중구조의 회전축 계 동특성을 해석할 수 있는 프로그램을 개발하므로서 회전 기계류의 진동 전반에 걸친 문제점에 대한 그 원인과 현상을 명확히 분석하여 국내의 전기 계류의 보다 신뢰성있는 설계 및 제작자료를 확보하는데 기여할 수 있게 하 였다.존의 small molecular Gd-chelate에 비해 매우 큼을 알 수 있었다. MnPC는 간세포에 흡수된 후 담도계로 배출되는 간특이성 조영제임을 확인하였다. 장비 내에서 반복 시행한 평균값의 차이는 대체적으로 유의한 차이가 없었으나, 다른 장비에서 반복 시행한 장비간의 사이에는 유의한 차이가 있는 경우가 더 많았다. 따라서 , MRS 검사를 소뇌나 뇌교의 어떤 절환에 적용하기 전에 각 장비 마다 정상 기준치를 반드시 얻은 후에 이상여부를 판 정하는 것이 필수적이라고 생각된다.EX> 이상이 적절한 진단기준으로 생각되었다. $0.4{\;}\textrm{cm}^3$ 이상의 좌우 부피차를 보이는 모든 증례에서 육안적으로도 해마위축이 뚜렷이 나타났다. 결론 : MR영상을 이용한 해마의 부피측정은 해마경화증 환자의 진단에 있어 육안적인 MR 진단이 어려운 제한된 경우에만 실제적 도움을 줄 수 있는 보조적인 방법으로 생각된다.ofile whereas relaxivity at high field is not affected by τS. On the other hand, the change in τV does not affect low field profile but strongly in fluences on both inflection fie이 and the maximum relaxivity value. The re

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.39-50
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• 2011

In this paper, we presents a CDR circuit for $2^{nd}$-generation AiPi+, one of the Intra-panel Interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with that of AiPi+. The DLL-based CDR architecture is used to generate the multi-phase clocks. We propose the simple scheme for frequency detector (FD) to mitigate the harmonic-locking and reduce the complexity. In addition, the duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatch between rising and falling time of VCDL's delay cells. The proposed CDR is implemented in 0.18 um technology with the supply voltage of 1.8 V. The active die area is $660\;{\mu}m\;{\times}\;250\;{\mu}m$, and supply voltage is 1.8 V. Peak-to-Peak jitter is less than 15 ps and the power consumption of the CDR except input buffer, equalizer, and de-serializer is 5.94 mW.

• Journal of the Korea Society of Computer and Information
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• v.17 no.12
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• pp.31-39
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• 2012

In this paper, we propose a microprocessor-based automatic voltage regulator(AVR) to reduce consumers' electric energy consumption and to help controlling peak demanding power. Hybrid Switching Automatic Voltage Regulator (HS-AVR) consist of a toroidal core, several tap control switches, display and command control parts. The coil forms an autotransformer which has a serial main winding and four parallel auxiliary windings. It controls the output voltage by changing the combination of the coils and the switches. Relays are adopted as the link switches of the coils to minimize the loss. To make connecting and disconnecting time accurate, relays of the circuit have parallel TRIACs. A software phase locked loop(PLL) has been used to synchronize the timings of the switches to the voltage waveform. The software PLL informs the input voltage zero-crossing and positive/negative peak timing. The traditional voltage transformers and AVRs have a disadvantage of having a large mandatory capacity to accommodate maximum inrush current to avoid the switch contact damage. But we propose a suitable AVR for every purpose in smart grid with reduced size and increased efficiency.

• Journal of Korea Water Resources Association
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• v.48 no.8
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• pp.613-623
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• 2015

To overcome the difficulties of discharge measurements during flood season, MWSCM(micowave water surface current meter) which measures river surface velocities without contacting water has been applied in field work since its development. The existing version of MWSCM is for floods so that its applicability is low due to the short periods of floods. Therefore the renovative redesign of MWSCM to increase the applicability was conducted so that it can be applied to the discharge measurements during normal flows as well as flood ones by extending the measurable range of velocity. A newly developed high-performance MWSCM for general use can measure the velocity range of 0.03-20.0 m/s from flood flows to normal flows, whereas MWSCM for floods can measure the velocity range of 0.5-10.0 m/s. The improvement of antenna isolation between transmitter and receiver to block the inflow of transmitted singals to receiver and the improvement of phase noise of oscillator are necessary for detecting low velocity with MWSCM technology. Separate type antenna of transmitting and receiving signals is developed for isolation enhancement and phase locked loop synthesizer as an oscillator is applied to high-performance MWSCM for general use. Microwave frequency of 24 GHz is applied to the new MWSCM rather than 10 GHz to make the new MWSCM small and light for convenient use of it at fields. Improvement requests on MWSCM for floods-stable velocity measurement, self test, low power consumtion, and waterproof and dampproof-from the users of it has been reflected on the development of the new version of MWSCM.