• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.8
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• pp.2055-2062
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• 1996

This paper presents a method of compensating for the gain and phase imbalance of quadrature modulator and demodulator. The gain and phase imbalance are compensated using the received power after the compensation pattern was transmitted at tranceiver. The proposed method is less vulnerable to changes in the transmission channel than the conventional method because compensation is made possible within the tranceiver system, and even the change in phase mblance in accordance with frequency can be compensated utilizing the adaptive algorithm. According to numerical results, a normalized eye opening and a bit error rate are improved by 1.8dB and 3.8dB, respectively.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.179-182
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• 1998

Carrier recovery, the process of recoverying the carrier in receiver, removes the phase difference between VCO and the received signal. However, the conventional structure of carrier recovery cannot be applied to multi-level QAM demodulator because of the increasing decision interval and the complexity of control as the number of symbol increases. In this paper, we suggest a new carrier recovery algorithm using $\theta-matching$ algorithm for multi-level QAM demodulation to overcome this problem and analysis the performance and implement it.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.226-230
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• 2000

In this paper, we implemented the QPSK demodulator with a CPLD chip, and examined the results. DD(Decision Directed)-Gardner algorithm is used for STR loop and Decision-Directed algorithm is used for CPR loop. The speed of the QPSK demodulator implemented in FLEX10K chip can be guaranteed approximately 2[Mbpsl] transmission speed. In practical designed by ASIC, the speed is faster than that of CPLD by 5-6 times.

• Korean Journal of Optics and Photonics
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• v.12 no.5
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• pp.371-375
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• 2001

We have implemented a sensor head which consists of erbium doped fiber pumped by 1480 nm LD and single fiber Bragg grating for simultaneous measurement of strain and temperature. The measurement precision and speed are improved by using Mach-Zehnder interferometer instead of optical spectrum analyzer (OSA) as a demodulator. The measurement precision of temperature measured by the amplitude variation of output signal is 0.05$^{\circ}C$ and that of strain measured by the phase variation of output signal is 0.1$\mu$strain. The measurement precision of temperature and strain are improved nearly 140 times and 700 times, respectively, compared to those using an OSA with wavelength resolution of 0.97 nm as d demodulator.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.10 no.2
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• pp.77-83
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• 2011

In this paper, we present the design procedure of the synchronizer and the demodulator of a 13.56MHz RFID PJM tag, which was standardized in ISO 18000-3 mode 3. We optimize the algorithms in order to minimize the number of registers and implement them based on international standard. The designed module is simulated by Modelsim and FPGA. The synchronizer is composed of 3 correlators that is implemented by 1,024(16bit ${\times}$ 64cycle) registers. The demodulator is composed of 2 correlators that is implemented by 128(2bit ${\times}$ 64cycle) registers. The simulation performed with the demodulator integrated with the synchronizer shows that it works at about 87% success rate with the test data of SNR -2dB and 100% with those of SNR 4dB.

• Journal of Korea Society of Industrial Information Systems
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• v.8 no.1
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• pp.83-91
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• 2003

High-speed QPSK demodulator has been in important design objective of any wireless communication systems, especially those offering broadband multimedia service. This paper describes all-digital QPSK demodulator for high-speed wireless communications, and its hardware structures are discussed. All-digital QPSK demodulator is mainly composed of symbol time circuit and carrier recovery circuit to estimate timing and phase-offsets. There are various schemes. Among them, we use Gardner algorithm and Decision-Directed carrier recovery algorithm which is most efficient scheme to warrant the fast acquisition and tacking to fabricate FPGA chip. The testing results of the implemented onto CPLD-EPF10K100GC 503-4 chip show demodulation speed is reached up to 2.6[Mbps]. If it is implemented a CPLD chip with speed grade 1, the demodulation speed can be faster by about 5 times. Actually in case of designing by ASIC, its speed my be faster than CPLD by 5 times. Therefore, it is possible to fabricate the all-digital QPSK demodulator chipset with speed of 50[Mbps].

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.12
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• pp.1248-1255
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• 2003

High-speed QPSK demodulator has been one important design objective of any wireless communication systems, especially those offering broadband multimedia service. This paper describes Zero-Crossing IF-level(ZCIF) QPSK demodulator for high-speed wireless communications, and its hardware structures are discussed. ZCIF QPSK demodulator is mainly composed of symbol time circuit and carrier recovery circuit to estimate timing and phase-offsets. There are various schemes. Among them, we use Gardner algorithm and Decision-Directed carrier recovery algorithm which is most efficient scheme to warrant the fast acquisition and tracking to fabricate FPGA chip. The testing results of the implemented onto CPLD-FLEX10K chip show demodulation speed is reached up to 2.6［Mbps］. Actually in case of designing by ASIC, its speed may be faster than CPLD by 5 times. Therefore, it is possible to fabricate the ZCIF QPSK demodulator with speed of 10 Mbps.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.1
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• pp.8-14
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• 1999

The active devices used at microwave frequency have the different phase shift according to input power. Especially, The difference of the phase shift is large in the saturation region of the amplifier. In this paper, we disigned the phase control system for fixing the different phase shift at device. With the high frequency nonlinear amplifier, we fabricated such system that the phase shift to be fixed automatically using the varible phase shifter. The variable phase shifter fixed total phase variation of the circuit using the information that was obtained from the comparison of imputsignal phase with output signal phase. Even though the input signal is 2-tone or FM type, we could estimate and also fix the phase variation on DUT Dynamic range is about 10dB. It has been experimented at 1960MHz using Teflon (H=31mil, ${\varepsilon}r$=3.2)

• Transactions on Electrical and Electronic Materials
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• v.11 no.1
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• pp.20-23
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• 2010

The analog front end (AFE) of a radio frequency identification transponder using the ISO 14443 type A standard with a 100% amplitude shift keying (ASK) modulation is proposed in this paper and verified by circuit simulations and measurements. This AFE circuit, using a 13.56 MHz carrier frequency, consists of a rectifier, a modulator, a demodulator, a regulator, a power on reset, and a dynamically enabled digital phase locked loop (DPLL). The DPLL, with a charge pump enable circuit, was used to recover the clock of a 100% modulated ASK signal during the pause period. A high voltage lateral double diffused metal-oxide semiconductor transistor was used to protect the rectifier and the clock recovery circuit from high voltages. The proposed AFE was fabricated using the $0.18\;{\mu}m$ standard CMOS process, with an AFE core size of $350\;{\mu}m\;{\times}\;230\;{\mu}m$. The measurement results show that the DPLL, using a demodulator output signal, generates a constant 1.695 MHz clock during the pause period of the 100% ASK signal.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.3
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• pp.81-86
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• 2010

Since CORDIC (COordinate Rotation DIgital Computer) is able to carry out the phase operation, such as vector to phase conversion or rotation of vectors, with adders and shifters, it is well suited for the design of the frequency synchronization unit in OFDM receivers. It is not easy, however, to fully utilize the CORDIC in the OFDM demodulator because of the non-linear characteristics of the direction sequence (DS), which is the representation of the phase in CORDIC. In this paper a new representation method is proposed to linearize the direction sequence approximately. The maximum phase error of the linearized binary direction sequence (LBDS) is also discussed. For the purpose of designing the hardware, the architectures for the binary DS (BDS) to LBDS converter and the LBDS to BDS inverse converter are illustrated. Adopting LBDS, the overall frequency synchronization hardware for OFDM receivers can be implemented fully utilizing CORDIC and general arithmetic operators, such as adders and multipliers, for the phase estimation, loop filtering of the frequency offset, derotation for the frequency offset correction. An example of the design of 22 bit LBDS for the T-DMB demodulator is also presented.