• Title/Summary/Keyword: Phase correction

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Correction of Accelerogram in Frequency Domain (주파수영역에서의 가속도 기록 보정)

  • Park, Chang Ho;Lee, Dong Guen
    • KSCE Journal of Civil and Environmental Engineering Research
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    • v.12 no.4
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    • pp.71-79
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    • 1992
  • In general, the accelerogram of earthquake ground motion or the accelerogram obtained from dynamic tests contain various errors. In these errors of the accelerograms, there are instrumental errors(magnitude and phase distortion) due to the response characteristics of accelerometer and the digitizing error concentrated in low and high frequency components and random errors. Then, these errors may be detrimental to the results of data processing and dynamic analysis. An efficient method which can correct the errors of the accelerogram is proposed in this study. The correction of errors can be accomplished through four steps as followes ; 1) using an interpolation method a data form appropriate to the error correction is prepared, 2) low and high frequency errors of the accelerogram are removed by band-pass filter between prescribed frequency limits, 3) instrumental errors are corrected using dynamic equilibrium equation of the accelerometer, 4) velocity and displacement are obtained by integrating corrected accelerogram. Presently, infinite impulse response(IIR) filter and finite impulse response (FIR) filter are generally used as band-pass filter. In the proposed error correction procedure, the deficiencies of FIR filter and IIR filter are reduced and, using the properties of the differentiation and the integration of Fourier transform, the accuracy of instrument correction and integration is improved.

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A 3-GSymbol/s/lane MIPI C-PHY Transceiver with Channel Mismatch Correction Circuit (채널 부정합 보정 회로를 가진 3-GSymbol/s/lane MIPI C-PHY 송수신기)

  • Choi, Seokwon;Song, Changmin;Jang, Young-Chan
    • Journal of IKEEE
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    • v.23 no.4
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    • pp.1257-1264
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    • 2019
  • A 3-GSymbol/s/lane transceiver, which supports the mobile industry processor interface (MIPI) C-physical layer (PHY) specification version 1.1, is proposed. It performs channel mismatch correction to improve the signal integrity that is deteriorated by using three-level signals over three channels. The proposed channel mismatch correction is performed by detecting channel mismatches in the receiver and adjusting the delay times of the transmission data in the transmitter according to the detection result. The channel mismatch detection in the receiver is performed by comparing the phases of the received signals with respect to the pre-determined data pattern transmitted from the transmitter. The proposed MIPI C-PHY receiver is designed using a 65 nm complementary metal-oxide-semiconductor (CMOS) process with 1.2 V supply voltage. The area and power consumption of each transceiver lane are 0.136 ㎟ and 17.4 mW/GSymbol/s, respectively. The proposed channel mismatch correction reduces the time jitter of 88.6 ps caused by the channel mismatch to 34.9 ps.

Evaluation Technique of Linearity of Ratio Error and Phase Angle Error of Voltage Transformer Comparison Measurement System Using Capacitor Burden (전기용량 부담을 이용한 전압변성기 비교 측정 시스템의 비오차 및 위상각 오차의 직선성 평가기술)

  • Jung Jae Kap;Kim Han Jun;Kwon Sung Won;Kim Myung Soo
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.54 no.6
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    • pp.274-278
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    • 2005
  • Voltage transformer(VT) comparison measurement system is usually used for measurements of ratio error and phase angle error of VT made in industry. Both ratio error and phase angle error in VT are critically influenced by values of burden of VT used. External burden effects on both ratio error and phase angle error in VT are theoretically calculated. From the theoretical calculation, a method of evaluation for linearity of ratio error and phase angle error in VT measurement system have been developed using the standard capacitive burdens, with negligible dissipation factor less than 10$^{-4}$. These burden consists of five standard capacitors, with nominal capacitance of 1.1 $\mu$F, 1 $\mu$F, 0.1 $\mu$F, 0.01 $\mu$F, 0.001 $\mu$F. The developed method has been applied in VT measurement system of industry, showing in good consistency and linearity within 0.001 $\%$ between theoretical and measured values.

Three-Phase Current Source Type ZVS-PWM Controlled PFC Rectifier with Single Active Auxiliary Resonant Snubber and Its Feasible Evaluations

  • Masayoshi Yamamoto;Shinji Sato;Tarek Ahmed;Eiji Hiraki;Lee, Hyun-Woo;Mutsuo Nakaoka
    • KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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    • v.4B no.3
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    • pp.127-133
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    • 2004
  • This paper presents a prototype of three-phase current source zero voltage soft-switching PWM controlled PFC rectifier with Single Active Auxiliary Resonant Commutated Snubber (ARCS) circuit topology. The proposed three-phase PFC rectifier with sinewave current shaping and unity power factor scheme can operate under a condition of Zero Voltage Soft Switching (ZVS) in the main three phase rectifier circuit and zero current soft switching (ZCS) in auxiliary snubber circuits. The operating principle and steady-state performances of the proposed three-phase current source soft-switching PWM controlled PFC rectifier controlled by the DSP control implementation are evaluated and discussed on the basis of the experimental results of this active rectifier setup.

Digital Current Control Scheme for Boost Single-Phase PFC Converter Based on Virtual d-q Transformation (가상 d-q 변환을 이용한 승압형 단상 PFC 컨버터의 디지털 전류 제어 방법)

  • Lee, Kwang-Woon;Kim, Hack-Jun
    • The Transactions of the Korean Institute of Power Electronics
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    • v.25 no.1
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    • pp.54-60
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    • 2020
  • A digital current control scheme using virtual d-q transformation for a boost single-phase power factor correction (PFC) converter is proposed. The use of virtual d-q transformation in single-phase power converters is known to improve current control performance. However, the conventional virtual d-q transformation-based digital current control scheme cannot be directly applied to the boost single-phase PFC converter because the current and average voltage waveforms of the inductor used in the converter are not sinusoidal. To cope with this problem, this study proposes a virtual sinusoidal signal generation method that converts the current and average voltage waveform of the inductor into a sinusoidal waveform synchronized with the grid. Simulation and experimental results are provided to show that the virtual d-q transformation-based digital current control is successfully applied to the boost single-phase PFC converter with the aid of the proposed virtual sinusoidal signal generation method.

Overview of Tidal Phase-lag References Used in Korea (우리나라 조석지각 기준 표기에 대한 고찰)

  • Byun, Do-Seong
    • The Sea:JOURNAL OF THE KOREAN SOCIETY OF OCEANOGRAPHY
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    • v.12 no.3
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    • pp.234-238
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    • 2007
  • Three different tidal phase-lag references have been used by the tidal research community of Korea: Greek kappa (k), Local standard time zone ($135^{\circ}E$) phase-lag (g) and Greenwich phase-lag (G). This ununified tidal information system may induce confusion in understanding tidal characteristics and their variability and impede the development of tidal knowledge in Korea. In this study we closely explore the three phase-lag reference definition with respect to their mutual conversion. We also identify an incorrect phase-lag reference definition used in previous works and discuss what has led to this misunderstanding.

A Novel PCCM Voltage-Fed Single-Stage Power Factor Correction Full-Bridge Battery Charger

  • Zhang, Taizhi;Lu, Zhipeng;Qian, Qinsong;Sun, Weifeng;Lu, Shengli
    • Journal of Power Electronics
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    • v.16 no.3
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    • pp.872-882
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    • 2016
  • A novel pseudo-continuous conduction mode (PCCM) voltage-fed single-stage power factor correction (PFC) full-bridge battery charger is proposed in this paper. By connecting a freewheeling transistor in parallel with an input inductor, the PFC cell can operate in the PCCM with a constant duty ratio. Thus, the dc/dc stage can be designed using this constant duty ratio and the restriction on the duty ratio of the PFC cell is eliminated. As a result, the input current distortion is less and the dc bus voltage becomes controllable over the wide output power range of the battery charger. Moreover, the operation principle of the dc/dc stage is designed to be similar to that of a conventional phase-shifted full-bridge converter. Therefore, it is easy to implement. In this paper, the operation of the new converter is explained, and the design considerations of the controller and key parameters are presented. Simulation and experimental results obtained from a 1 kW prototype are given to confirm the operation of the proposed converter.

A Study on Super Resolution Optimum Beam Steering Pattern for Improvement Moving Target Estimation Accuracy (이동 목표물 추정 정확도를 향상시키기 위한 고 분해능 최적 빔 지향 패턴에 관한 연구)

  • Cho, Sung Kuk;Jeon, Byung Kook;Yang, Gill Mo
    • Journal of Korea Society of Digital Industry and Information Management
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    • v.10 no.4
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    • pp.71-78
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    • 2014
  • Method a target estimation in spatial are mobile wireless communication using network cell and GPS. It have much error that mobile wireless communication depend on cell size. GPS method can't find a target in shadow and inner area. In this paper, we estimate a target as direction of arrival method using adaptive array antenna system. Adaptive array antenna system can obtain desired signal to remove other signal This paper studied digital beamforming method in order to estimation a target. Proposed method is modified optimum weight and antenna error correction to estimation an optimal receive signal. Digital beamforming method decided a signal phase and amplitude from received signal on array antenna element. But if it is not to do error correction of received signal, system performance have decreased. Firstly, we proposed modified optimum weight in order to finding desired target. Secondly, we are error correction of antenna incident signals by optimal weight before digital beamforming method. Thirdly, throughly simulation, we showed that system performance of proposed method compare proposal method with general method. It have improved resolution of estimation target to good performance more proposed method than general method.

Microcontroller based Single-phase SRM Drive with High Power Factor (마이크로 콘트롤러기반의 고역률형 단상 SRM 구동)

  • Ahn, Jin-Woo;Lee, Zhen-Guo
    • The Transactions of the Korean Institute of Power Electronics
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    • v.11 no.1
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    • pp.90-96
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    • 2006
  • A novel high power factor drive of a single-phase switched reluctance motor (SRM) is researched. It achieves sinusoidal and near unity power factor input currents. The proposed SRM drive has one additional active switches. And a single-stage approach has a simple structure and low cost. A prototype to drive an SRM equipping a suitable encoder is designed to evaluate the proposed topology. The characteristics and validity of the proposed circuit is discussed with some simulations and experimental results.

A PSpice Modeling of PFC Circuit Using Soft-Switched Boost Converter

  • Mok, H.S.;Choe, G.H.;Jeong, S.E.;Choi, J.Y.
    • Proceedings of the KIPE Conference
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    • 1997.07a
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    • pp.393-399
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    • 1997
  • Single-phase and three-phase AC to DC power converters are becoming frequently used for high voltage/high power applications such as telecommunications. They often require input/output transformer isolation for safety, a unity input power factor for minimum reactive power, free input harmonic currents fed back to the AC Power distribution system and, finally, high efficiency and high power density for minimum weight and volume. The proposed boost converter for power factor correction (PFC) provides an unity input power factor, low harmonic distortion and high efficiency along with reduced volume and weight. Single-phase 220VAC input/380VDC 1KW output prototype is constructed and experimental results will be verified with those of PSpice simulation.

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