Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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A 3-GSymbol/s/lane MIPI C-PHY Transceiver with Channel Mismatch Correction Circuit

채널 부정합 보정 회로를 가진 3-GSymbol/s/lane MIPI C-PHY 송수신기

  • Choi, Seokwon (Department of Electronic Engineering, Graduate School, Kumoh National Institute of Technology) ;
  • Song, Changmin (Department of Electronic Engineering, Graduate School, Kumoh National Institute of Technology) ;
  • Jang, Young-Chan (Department of Electronic Engineering, Graduate School, Kumoh National Institute of Technology)
  • Received : 2019.12.09
  • Accepted : 2019.12.26
  • Published : 2019.12.31
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Abstract

A 3-GSymbol/s/lane transceiver, which supports the mobile industry processor interface (MIPI) C-physical layer (PHY) specification version 1.1, is proposed. It performs channel mismatch correction to improve the signal integrity that is deteriorated by using three-level signals over three channels. The proposed channel mismatch correction is performed by detecting channel mismatches in the receiver and adjusting the delay times of the transmission data in the transmitter according to the detection result. The channel mismatch detection in the receiver is performed by comparing the phases of the received signals with respect to the pre-determined data pattern transmitted from the transmitter. The proposed MIPI C-PHY receiver is designed using a 65 nm complementary metal-oxide-semiconductor (CMOS) process with 1.2 V supply voltage. The area and power consumption of each transceiver lane are 0.136 ㎟ and 17.4 mW/GSymbol/s, respectively. The proposed channel mismatch correction reduces the time jitter of 88.6 ps caused by the channel mismatch to 34.9 ps.

본 논문에서는 모바일 산업 프로세서 인터페이스(MIPI:mobile industry processor interface)의 C-PHY 사양 버전 1.1을 지원하는 3-GSymbol/s/lane 송수신기가 제안된다. 제안한 송수신기는 3 개 채널에서 3 개 레벨 신호의 사용으로 인해 저하된 신호 보존성을 개선하기 위해 채널 부정합 보정을 수행한다. 제안된 채널 부정합 보정은 수신기에서 채널 부정합을 검출하고, 검출 결과에 따라 송신기에서 전송 데이터의 지연 시간을 조정함으로써 수행된다. 수신기에서 채널 불일치 검출은 송신기로부터 전송된 정해진 데이터 패턴에 대하여 수신된 신호의 위상을 비교함으로써 수행된다. 제안된 MIPI C-PHY 송수신기는 1.2 V 공급 전압의 65 nm CMOS 공정을 사용하여 설계되었다. 각 송수신기 레인의 면적과 전력소모는 각각 0.136 ㎟와 17.4 mW/GSymbol/s이다. 제안된 채널 부정합 보정은 채널 부정합으로 인한 88.6 ps의 시간 지터를 34.9 ps로 줄인다.

Keywords

References

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