• 제목/요약/키워드: Phase Synchronization

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Time-Synchronization Method for Dubbing Signal Using SOLA (SOLA를 이용한 더빙 신호의 시간축 동기화)

  • 이기승;지철근;차일환;윤대희
    • Journal of Broadcast Engineering
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    • v.1 no.2
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    • pp.85-95
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    • 1996
  • The purpose of this paper Is to propose a dubbed signal time-synchroniztion technique based on the SOLA(Synchronized Over-Lap and Add) method which has been widely used to modify the time scale of speech signal. In broadcasting audio recording environments, the high degree of background noise requires dubbing process. Since the time difference between the original and the dubbed signal ranges about 200mili seconds, process is required to make the dubbed signal synchronize to the corresponding image. The proposed method finds he starting point of the dubbing signal using the short-time energy of the two signals. Thereafter, LPC cepstrum analysis and DTW(Dynamic Time Warping) process are applied to synchronize phoneme positions of the two signals. After determining the matched point by the minimum mean square error between orignal and dubbed LPC cepstrums, the SOLA method is applied to the dubbed signal, to maintain the consistency of the corresponding phase. Effectiveness of proposed method is verified by comparing the waveforms and the spectrograms of the original and the time synchronized dubbing signal.

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Measurement of Setup and Hold Time in a CMOS DFF for a Synchronizer (동기회로 설계를 위한 CMOS DFF의 준비시간과 유지시간 측정)

  • Kim, Kang-Chul
    • The Journal of the Korea institute of electronic communication sciences
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    • v.10 no.8
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    • pp.883-890
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    • 2015
  • As the semiconductor processing technology has been developing, multiple cores or NoC(network on chip) can be contained in recent chips. GALS(globally asychronous locally synchronous) clocking scheme that has multi-clock domains with different frequencies or phase differences is widely used to solve power consumption and clock skew in a large chip with a single clock. A synchronizer is needed to avoid a synchronization problem between sender and receiver in GALS. In this paper, the setup and hold time of DFF required to design the synchronizer are measured using 180nm CMOS processing parameters depending on temperature, supply voltage, and the size of inverter in DFF. The simulation results based on the bisection method in HSPICE show that the setup and hold time are proportional to temperature, however they are inversely proportional to supply voltage, and negative values are measured for the hold time.

Design of digital communication systems using DCSK chaotic modulation (DCSK 카오스 변조를 이용한 디지털 통신 시스템의 설계)

  • Jang, Eun-Young
    • The Journal of the Korea institute of electronic communication sciences
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    • v.10 no.5
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    • pp.565-570
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    • 2015
  • Spread spectrum communications have increased interest due to their immunity to channel fading and low probability of intercept. One of the limitations of the traditional digital spread spectrum systems is the need for spreading code synchronization. Chaotic communication is the analogue alternative of digital spread spectrum systems beside some extra features like simple transceiver structures. In this paper, This paper was used instead of the digital modulation and demodulation carriers for use in the chaotic signal in a digital communication system among the chaotic modulation schemes, the Differential Chaos Shift Keying(DCSK) is the most efficient one because its demodulator detects the data without the need to chaotic signal phase recovery. Also Implementation of Differential Chaos Shift Keying Communication System Using Matlab/Simulink and the receiver con decode the binary information sent by the transmitter, performance curves of DCSK are given in terms of bit-error probability versus signal to noise ratio with spreading factor as a parameter and we compare it to BPSK modulation.

PWM Synchronization and Phase-Shift Method using CAN Communication in Cascaded H-Bridge Multilevel Inverter (CAN통신을 이용한 H-브릿지 멀티레벨 인버터의 PWM 동기화 및 위상전이 방법)

  • Park Y. M.;Yoo H. S.;Jang S. Y.;Lee H. W.;Lee S. H.;Seo K. D.
    • Proceedings of the KIPE Conference
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    • 2004.07a
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    • pp.374-379
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    • 2004
  • H-브릿지 멀티레벨 인버터는 여러 개의 단상 Power Cell을 직렬로 연결함으로써 저전압 전력용 반도체를 사용하여 고전압을 얻을 수 있고, 정현파에 가까운 출력전압 파형을 얻을 수 있는 멀티레벨 인버터 토폴로지이다. 본 토폴로지는 출력전압 레벨에 비례하여 Power Cell의 수가 증가하므로, 주제어기의 연산능력에 대한 부담증가와 신호선의 많아지는 단점이 있다. 따라서 Power Cell제어를 직접적인 PWM 신호가 아닌 통신을 사용함으로써 이러한 단점을 극복할수 있으며, 신뢰성 측면이나 보수/유지 측면에서도 유리하다. 본 논문은 산업현장에서 신뢰성을 인정받아 많이 사용되고 있는 직렬통신 방식의 일종인 CAN통신 인터럽터를 이용한 H-브릿지 멀티레벨 인버터 Power Cell의 PWM 동기화 및 위상 전이 방법에 관한 것이다. 제안된 방법의 주요 장점은 주제어기와 셀 제어기 사이에 직렬통신(CAN)을 사용함으로써 주제어기와 셀 제어기의 신호선의 단순화, 주제어기의 부담 감소, Power Cell의 모듈화, 셀 단위의 보호동작 용이, 확장성 향상 그리고 제어 신호 및 Power Cell의 신뢰성을 향상에 있다. 13레벨로 구성된 H-브릿지 멀티레벨 인버터 시험을 통해 제안된 방법의 타당성과 신뢰성을 입증하였다.

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Trials to Increase the Availability of Ovsynch Program Under Field Conditions in Dairy Cows

  • Jeong, Jae-Kwan;Choi, In-Soo;Lee, Soo-Chan;Kang, Hyun-Gu;Hur, Tai-Young;Kim, Ill- Hwa
    • Journal of Veterinary Clinics
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    • v.33 no.4
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    • pp.200-204
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    • 2016
  • This study investigated whether presynchronization with GnRH 6 days before initiation of the Ovsynch program improved reproductive outcomes in dairy cows. Additionally, postponement of initiation of the Ovsynch program for cows during the metestrus phase by 5 days was investigated to determine if it improved reproductive outcomes. To accomplish this, 941 Holstein dairy cows with unknown estrous cycle were randomly allocated into an Ovsynch group (n = 768; $100{\mu}g$ gonadorelin [a GnRH analogue], $500{\mu}g$ of cloprostenol [$PGF_{2{\alpha}}$ analogue] seven days later, $100{\mu}g$ gonadorelin 56 h later and timed artificial insemination [AI] 16 h after) and a G6-Ovsynch (n = 173) that received $100{\mu}g$ GnRH followed by the Ovsynch program 6 days later. Additionally, 272 dairy cows with known estrous cycle (metestrus stage) received the Ovsynch 5 days later (Day 5-Ovsynch group, n = 272). The odds ratio (OR) for pregnancy was analyzed by logistic regression using the LOGISTIC procedure in SAS. The treatment group (p < 0.001) and AI season (p < 0.05) significantly affected the probability of pregnancy, whereas farm, cow parity, calving to AI interval, and body condition score had no affect (p > 0.05). The Day 5-Ovsynch group had a higher probability of pregnancy (OR: 1.71) than the Ovsynch group, while that of the G6-Ovsynch group was intermediate (p > 0.05). Cows inseminated during winter had a higher OR (1.39) than those inseminated during spring. Overall, additional GnRH treatment 6 days before the Ovsynch did not improve reproductive outcomes, whereas postponement of the initiation of Ovsynch by 5 days for cows during metestrus improved reproductive outcomes.

Estimation Techniques for Sampling Frequency Offset in OFDM Systems (OFDM 시스템의 샘플링 주파수 옵셋 추정기법)

  • 전원기;조용수
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.24 no.9B
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    • pp.1795-1805
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    • 1999
  • In an OFDM (Orthogonal Frequency-Division Multiplexing) system, the sampling frequency offset between the transmitter and receiver is known to cause the interchannel interference (ICI), resulting in performance degradation. In this paper, we propose two time-domain techniques to estimate the sampling frequency offset, especially for a high data-rate OFDM system. The first technique estimates the sampling frequency offset by using the phase difference between two received samples with a fixed amount of time interval, corresponding to the transmitted training symbol, under the assumption of perfect symbol and carrier offset synchronization. The second technique estimates the sampling frequency offset and carrier frequency offset jointly, when the two offsets exist together, by using two training symbols with different frequency components and using a sample algebraic calculation. The proposed estimation techniques for sampling frequency offset cause no time delay due to all time-domain processing, and have a good performance due to no ICI effect. The performances of the proposed techniques are demonstrated by various simulations.

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Efficient Hardware Support: The Lock Mechanism without Retry (하드웨어 지원의 재시도 없는 잠금기법)

  • Kim Mee-Kyung;Hong Chul-Eui
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.9
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    • pp.1582-1589
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    • 2006
  • A lock mechanism is essential for synchronization on the multiprocessor systems. The conventional queuing lock has two bus traffics that are the initial and retry of the lock-read. %is paper proposes the new locking protocol, called WPV (Waiting Processor Variable) lock mechanism, which has only one lock-read bus traffic command. The WPV mechanism accesses the shared data in the initial lock-read phase that is held in the pipelined protocol until the shared data is transferred. The nv mechanism also uses the cache state lock mechanism to reduce the locking overhead and guarantees the FIFO lock operations in the multiple lock contentions. In this paper, we also derive the analytical model of WPV lock mechanism as well as conventional memory and cache queuing lock mechanisms. The simulation results on the WPV lock mechanism show that about 50% of access time is reduced comparing with the conventional queuing lock mechanism.

Performance Analysis of a Receiver for WCDMA Systems (광대역 코드분할 다중화 시스템 수신기의 성능 분석)

  • 박중후
    • The Journal of the Acoustical Society of Korea
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    • v.20 no.6
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    • pp.87-93
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    • 2001
  • As a new type of a linear decorrelating receiver, the Pseudo-Decorrelator was presented for asynchronous code division multiple access systems by the author. In this paper, the concept of the Pseudo-Decorrelator is extended to derive a receiver for WCDMA uplink systems over an additive white Gaussian noise channel. Starting with the analysis of the multiple access components of the decision statistics, a non-square cross-correlation matrix for each bit is obtained. This cross-correlation matrix is then inverted, and the inverted matrix is applied to the decision statistics obtained from a conventional receiver. In this receiver, the detection process can be started after the first three consecutive bits are received. Simulation results are presented for K-user systems over an additive white Gaussian noise channel under the circumstances in which synchronization errors, including time delay errors and carrier phase errors exist. It is shown that the proposed receiver performs better than a conventional receiver and parallel interference canceller.

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Four-Dimensional Computed Tomography for Gated Radiotherapy: Retrospective Image Sorting and Evaluation

  • Lim, Sang-Wook;Park, Sung-Ho;Back, Geum-Mun;Ahn, Seung-Do;Shin, Seong-Soo;Lee, Sang-Wook;Kim, Jong-Hoon;Choi, Eun-Kyuong;Kwon, Soo-Il
    • Proceedings of the Korean Society of Medical Physics Conference
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    • 2005.04a
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    • pp.71-74
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    • 2005
  • To introduce the four-dimensional computed tomography (4DCT, Light Speed RT, General Electric, USA) scanner newly installed in our department and evaluate its feasibility for gated radiotherapy. Respiratory signal measured by real-time position management (RPM$^{\circledR}$, Varian Medical, USA) was recorded in synchronization with the 4DCT scanner. 4DCT data were acquired in axial cine mode and sorted retrospective image based on respiratory phase. PTVs delineated from helical CT and 4DCT images were compared. The PTV delineated from conventional helical CT images was 2 cc larger than that from 4DCT images. Dose in PTV of the plan from retrospective CT was 99.3% (minimum=72.0%, maximum=106.5%) and that of helical CT plan was 95.2% (minimum=24.1%, maximum=106.4%) of prescribed dose. Comparing with DVHs of both plan, the coverage for 4CDT plan was 3.7% improved. It is expected that 4DCT could improve tumor control and reduce radiation toxicity for liver cancer.

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The Circuit Design and Analysis of the Digital Delay-Lock Loop in GPS Receiver System (GPS 수신 시스템에서 디지탈 지연동기 루프 회로 설계 및 분석)

  • 금홍식;정은택;이상곤;권태환;유흥균
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.19 no.8
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    • pp.1464-1474
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    • 1994
  • GPS(Global Positioning System)is a satellite-based navigation system that we can survey where we are, anywhere and anytime. In this paper, delay-lock loop of the receiver which detects the navigation data is theoretically analyzed, and designed using the digital logic circuit. Also logic operations for the synchronization are analyzed. The designed system consists of the correlator which correlates the received C/A code and the generated C/A code in the receiver, the C/A code generator which generates C/A code of selected satellite, and the direct digital clock syntheizer which generates the clock of the C/A code generator to control the C/A code phase and clock rate. From the analyses results of the proposed digital delay-lock loop system, the system has the detection propertied over 90% when its input signal power is above-113.98dB. The influence of input signal variation of digital delay loop, which is the input of A/D converter, is investigated and the performance is analyzed with the variation of threshold level via the computer simulation. The logic simulation results show that the designed system detects precisely the GPS navigation data.

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