• 한국정보통신학회논문지
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• 제3권4호
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• pp.805-817
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• 1999

In this paper, the needs for introduction and adoption of MㆍHF DSC/NBDP system and for developments of its circuits and call sequences for use in the maritime mobile services for small-ships, leisure-ships and fishing ships are analyzed, discussed. Also design and implement for MㆍHF(1.6-4MHz) DSC/NBDP system is discussed. Most of casualties have been arisen from small-ships and fishing ships during last 5 years. So, the SAR schematic plans should been prepared to prevent casualties and facilitate the activities of SAR for those ships. DSC/NBDP for MㆍHF system is able to fulfill the roles of efficient SAR communication functions, and to advance the SAR system to small ships and fishing ships. This study is focused on the techniques of processing the DSC call sequences and the ARQ sequences of NBDP system. Especially ARQ sequences are expanded into processing of Korean letters, designed the call sequences and code conversion algorithm for Korean-code. It will be evaluated the availability of Korean-NBDP system. In designing the Transmitting circuits and Receiving circuits, for the carrier generation, DDS(Direct Digital Synthesizer) is used in stead of the Phase Locked Loop and frequency conversion by the mixer, BPF. And PSK modulation signals are directly generated by the controls of DDS, which show the characteristics of Spurious Free Dynamic Range are below -62dBc. Also, the monolithic U subsystem IC which provides various functional components, AD608 is used for designing the receiving circuitsㆍAnd the algorithm of Phasing methode for FSK demodulation are devised to process IF frequency 455kHz in the IF circuits.

• Journal of Power Electronics
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• 제16권4호
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• pp.1375-1386
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• 2016

To decouple the secondary saliencies in sensorless permanent magnet synchronous machine (PMSM) drives, a repetitive control (RC) in the angle domain is proposed. In this paper, the inductance model of a concentrated windings surface-mounted PMSM (cwSPMSM) with strong secondary saliencies is developed. Due to the secondary saliencies, the estimated position contains harmonic disturbances that are periodic relative to the angular position. Through a transformation from the time domain to the angle domain, these varying frequency disturbances can be treated as constant periodic disturbances. The proposed angle-domain RC is plugged into an existing phase-locked loop (PLL) and utilizes the error of the PLL to generate signals to suppress these periodic disturbances. A stability analysis and parameter design guidelines of the RC are addressed in detail. Finally, the proposed method is carried out on a cwSPMSM drive test-bench. The effectiveness and accuracy are verified by experimental results.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2007년도 춘계학술대회
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• pp.317-319
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• 2007

Recently, there were many researches for efficiency improvement of DSC. Among of these works, research of surface treatment is still a prerequisite for electron diffusion, light-harvesting and surface state of $DSC^{4)}$. Using of the surface treatment, it can be raise up porosity of $TiO_{2}$ nano-crystalline structure on $photo-electrode^{5)}$. There are chemical, physical, electrical and optical methods which raise up its porosity. In this paper, we have designed and manufactured MOPA-type ultrasonic circuit (100W, frequency and duty variable). Manufactured ultrasonic circuit to use to force cavity density and power into $TiO_{2}$ paste. Then, we have optimized forcing time, frequency and duty of ultrasonic irradiation for surface treatment of photo-electrode of DSC. In I-V characteristic test of DSC, ultrasonic and thermal treated DSC shows 19% improved its efficiency against established DSC.

• 대한전자공학회논문지TC
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• 제42권4호
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• pp.1-6
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• 2005

본 논문에서는 송신기와 수신기의 구현에 있어서 많은 장점을 제공하는 직접 확산-주파수(DSSS-FSK) 변조를 제안한다. 주파수 변조를 사용하여, 직접 확산 통신에서도 주파수합성기(PLL)를 이용한 송신기의 구현이 가능하므로 저전력, 저가격이 가능하다. 또한, 반송과 인접 대역에 정보를 전송하지 않아서 직접변환방식 수신기(DCR)의 구현을 용이하게 한다 한편, DSSS-FSK 신호를 위한 최적 동기 검파와 반동기 상관 검파 구조를 제안하고 그 성능을 분석한다. 매우 큰 반송파 주파수오프셋에서도 우수한 비트오율성능을 가지기 위해서, 분할 반동기 상관 검파 구조를 제안하고 성능을 분석한다.

• 대한전자공학회논문지SD
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• 제45권8호
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• pp.44-47
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• 2008

본 논문에서는 UWB PLL charge pump 의 충/방전 전류오차를 최소화하기 위한 회로를 제안하였다. Common-gate 와 Common-source 증폭기를 추가한 피드백 전압 조정기를 구성하여 높은 응답성을 가지는 charge pump를 설계하였다. 제안한 회로는 넓은 동작 영역을 갖으며, 낮은 전원 전압으로도 뛰어난 성능을 보인다. 본 회로는 1.2V 공급 전압과 IBM 0.13um CMOS 공정으로 집적되었다. 설계의 효율성을 평가하기 위해 참고 논문의 다른 회로와 성능을 대조하였다.

• ETRI Journal
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• 제29권4호
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• pp.421-429
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• 2007

This paper presents a direct-conversion CMOS transceiver for fully digital DS-UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase-locked loop (PLL), and a voltage controlled oscillator (VCO). A single-ended-to-differential converter is implemented in the down-conversion mixer and a differential-to-single-ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 $mm^2$ die using standard 0.18 ${\mu}m$ CMOS technology and a 64-pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low-power, and high-speed wireless personal area network.

• Journal of Advanced Marine Engineering and Technology
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• 제36권1호
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• pp.166-171
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• 2012

본 논문에서는 가시광 LED를 이용한 근거리 수중 광무선 통신 기술을 제안하였다. 수중 통신을 위한 기존 음향 시스템의 대안으로 부상하는 가시광 LED 통신은 고품질의 높은 통신 속도를 보장한다. 수중에서 근거리 통신을 위하여 주파수 변조 방식을 적용한 광 무선 오디오 시스템을 개발하였으며 CD4046B 위상잠김루프를 이용하여 주파수 변조와 복조 회로 부분을 구현하였다. 수조내에서 송신단과 수신단을 30 cm 떨어뜨린 후 100 kHz의 변조 중심 주파수에서 오디오 신호를 전송하여 성공적으로 수신됨을 확인하였다.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2003년도 종합학술발표회 논문집 Vol.13 No.1
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• pp.136-139
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• 2003

A clock recovery circuit for a 40 Gb/s optical receiver has been designed and implemented. The clock recovery circuit consists of signal amplifiers, a nonlinear circuit with diodes, and a bandpass filter Before implementing the 40 Gb/s clock recovery circuit, a 10 Gb/s clock recovery circuit has been successfully implemented and tested. With the 40 Gb/s clock recovery circuit, when a 40 Gb/s NRZ signal of -10 dBm was applied to the input of the circuit, the 40 GHz clock was recovered with the -20 dBm output power after passing through the nonlinear circuit. The output signal from the nonlinear circuit passes through a narrow-band filter, and then amplified. The implemented clock recovery circuit is planned to be used for the input of a phase locked loop to further stabilize the recovered clock signal and to reduce the clock jitter.

• 전기학회논문지
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• 제64권3호
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• pp.433-437
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• 2015

We have designed and fabricated a low power and high linearity up down convertor for wireless repeaters using $0.35{\mu}m$ SiGe Bipolar CMOS technology. Repeater is composed of a wideband up/down converting mixer, programmable gain amplifiers (PGA), input buffer, LO buffer, filter driver amplifier and integer-N phase locked loop (PLL). As of the measurement results, OIP3 of the down conversion mixer and up conversion mixer are 32 dBm and 17.8 dBm, respectively. The total dynamic gain range is 31 dB with 1 dB gain step resolution. The adjacent channel leakage ratio (ACLR) is 59.9 dBc. The total power consumption is 240 mA at 3.3 V.

• 전기학회논문지
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• 제61권12호
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• pp.1848-1856
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• 2012

This paper proposes a new grid-tied power conditioning system for battery energy storage, which is composed of a 2-stage DC-DC converter and a PWM inverter. The 2-stage DC-DC converter is composed of an LLC resonant converter connected in cascade with a 2-quadrant hybrid-switching chopper. The LLC resonant converter operates in constant duty ratio, while the 2-quadrant hybrid-switching chopper operates in variable duty ratio for voltage regulation. The operation of proposed system was verified through theoretical analysis and computer simulations. Based on computer simulations, a hardware prototype was built and tested to confirm the technical feasibility of proposed system. The proposed system could have relatively higher efficiency and smaller size than the existing system.