• Proceedings of the KIEE Conference
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• 1997.07c
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• pp.1048-1051
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• 1997

본 논문에서는 GPS 수신기를 이용하여 송전선 양단에 설치되어 있는 전류차동계전기들의 전류샘플링을 동기시키는 방법을 제안하고, 이를 이용한 전류샘플링 동기장치의 개발에 대해 설명 한다. 송전선 양단의 GPS 수신기들에서 만들어지는 서로 동기된 IPPS신호들을 이용해 샘플링 동기신호를 만들어 주고, 이를 이용해서 서로 동기된 전류샘플링이 적당한 계수값 지정과 함께 이루어지도록 A/D변환기와 메모리 그리고 프로그램형 논리 소자를 사용한다. 샘플링 동기신호를 만들어주기 위해서 GPS수신기와 10MHz발진기를 이용한 디지털 위상잠금회로(DPLL, Digital Phase- Locked Loop)를 구성 한다. 본 논문에서 제안하는 전류샘플링 동기방식은 통신을 이용한 기존의 방식에 비해 계전기의 계산부담을 덜어주고 보다 정확한 샘플링 동기를 얻을 수 있게 한다.

• Proceedings of the KIEE Conference
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• 2004.10a
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• pp.224-226
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• 2004

Digital Kalman filter is presented as a powerful approach to obtain the reference estimation of the control current for shunt active power filter. This algorithm provides the best estimate of the fundamental and harmonic frequency components from the sampled values of the line current or voltage. By adopting of the digital Kalman filtering algorithm, the structure of the control algorithm eliminates the need of a Phase locked loop(PLL) for the synchronization of the reference signal used in the compensation and it not sensitive to the distortion of the line voltage. The effectiveness of the algorithm is confirmed by the computer simulations.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.308-310
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• 2008

향후 가까운 미래에 정부에서 주도하고 있는 10만호 보급사업 등을 포함한 대규모 태양광발전산업의 보급에 따라 특정지역에서는 계통연계형 태양광 전력변환기(PV PCS)의 고밀도 연계가 예상된다. 이 때 지금까지는 이론적으로만 가능할 것으로 여겨졌던 현상 인 단독운전 현상이 발생할 수 있는 확률이 높아지게 된다. 본 논문에서는 전력변동기법 중 하나인 무효전력변동기법에 대하여 단독운전검출 성능을 향상시키기 위한 한 방법으로 Digital Phase-Locked-Loop(DPLL)의 주파수계산을 이용하여 그 효용성을 PSIM 시뮬레이션을 통하여 검증하였다.

• Proceedings of the KSR Conference
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• 2004.10a
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• pp.1480-1485
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• 2004

In this paper, a real-time digital kalman filtering algorithm is used to obtain the reference estimation of the control current for shunt active power filter. This algorithm provides the best estimate of the fundamental and harmonic frequency components from the sampled values of the line current or voltage waveform. By adopting of the digital Kalman filtering algorithm, the structure of the control algorithm eliminates the need of a Phase locked loop(PLL) for the synchronization of the reference signal used in the compensation and it not sensitive to the distortion of the line voltage. The effectiveness of the algorithm is confirmed by the computer simulations.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.47-54
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• 1996

In this paper we propose a new timing recovery method by means of utilizing service data filling rate instead of timing information of transmitter. A proposed algorithm controls the phase locked loop in the opposite direction ot data filling rate of FIFO in receiver, and it is based on the fact that average of cell jitters is zero. The proposed method is simple compared with timing information method of transmitter. It can be utilized for timing recovery in synchronous digital hierarchy as well as in plesiochronous digial hierarchy without common reference clocks in end-to-end erminals. We implement the interactive video communication system and test the proposed algorithm. As a result, we hav econfirmed that it yields good perfomrnces in terms of jitters characteristics and hardware complexity.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.963-964
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• 2006

By combining a digital DLL and an analog DLL in 2-stage, an improved DLL is implemented in this paper. The proposed DLL is composed of a RDLL (Register Controlled DLL) and a conventional analog DLL. The phase comparator used in the DLL is built with sense-amp based D flip-flops for high speed operation. The proposed DLL circuits have been designed, simulated in 0.18um, 1.8V TSMC CMOS library. The implemented DLL have demonstrated the fast lock-on time of 1us and low jitter of 72ps.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.605-606
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• 2006

Voltage Controlled Oscillator(VCO) plays an important role in today's communication systems. Especially, a Clock Generator(CG) in phase-locked loop(PLL) is usually realized by the VCO. This paper proposes a new VCO with a controllable duty cycle buffer, that can be adopted in low-power high-speed communication systems. Delay cell of the VCO is implemented with gilbert cell. Frequency dynamic range of the VCO is in the range of approximately $50MHz{\sim}500MHz$. Parameters with N-well CMOS 0.18-um process with 1.8V supply voltage was used for the simulations.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.415-424
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• 2016

This paper describes a high data rate proximity transmitter design for high resolution smartphone-mirrored display applications. A 2 Gb/s transmitter is designed with a low transmission power of -70 dBm/MHz and a wide bandwidth of nearly 3 GHz. A digital pre-correction method is employed in the transmitter to mitigate the inter-symbol interference problem. A carrier-based digital pulse shaping and a reconfigurable digital envelope generation methods are employed for robust operation by utilizing 20 phases from a 2 GHz phase-locked loop. A 6.5-9.5 GHz transmitter implemented in 65 nm CMOS achieves the maximum data rate of 2 Gb/s, consuming only 7.6 mW from a 1 V supply.

• Journal of Electrical Engineering and Technology
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• v.7 no.3
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• pp.358-365
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• 2012

A new third harmonic injection circuit for light-emitting diode (LED) drivers is proposed to eliminate electrolytic capacitors and thereby extend the lifetime of LED drivers. When a third harmonic current is injected to the input current of the LED driver, the required capacitance of the driver can be reduced. The proposed circuit can control an injection ratio and has simple circuitry. The synchronous third harmonic is generated by a phase locked loop (PLL), a 1/3 counter, and op-amps and applied to a power factor correction circuit. Thus, the storage capacitor can install film capacitors instead of the electrolytic capacitor. The value of storage capacitance can be reduced to 78% compared to an input power factor of 100%. The proposed circuit is applied to the 80W prototype LED driver to experimentally verify the performances.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.691-693
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• 2017

A novel structure of fast locking phase locked loop (PLL) with time difference detector and Lock status indicator (LSI) is proposed in this paper. Fast locking time is achieved using LSI. It has been simulated and proved by HSPICE in a CMOS $0.18{\mu}m$ 1.8V process.