• Title/Summary/Keyword: Path extraction

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Evaluation of Remediation of Contaminated Soil Using PVDs (연직배수재를 이용한 오염도턍복원 특성 평가)

  • Shin, Eun-Chul;Park, Jeong-Jun;Roh, Jeong-Min
    • Proceedings of the Korean Geotechical Society Conference
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    • 2005.03a
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    • pp.1400-1407
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    • 2005
  • There are a number of approaches to in situ remediation that are used at contaminated sites for removing contaminants from the contaminated zone without excavating the soil. These include soil flushing, dual phase extraction, and soil vapor extraction. Of these techniques, soil flushing is the focus of the investigation in this paper. The concept of using prefabricated vertical drains(PVDs) for remediation of contaminated sites with fine-grained soils is examined. The PVD system is used to shorten the drainage path or the groundwater flow and promote subsurface liquid movement expediting the soil flushing process. The use of PVDs in the current state of practice has been limited to soil improvement. The use of PVDs under vacuum conditions is investigated using sample soil consisting of silty sand.

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Chip Pin Parasitic Extraction by Using TDR and NA (TDR 및 NA를 이용한 Chip Pin Parasitic 추출)

  • 이현배;박홍준
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.899-902
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    • 2003
  • Chip Pin Parasitic은 실제 Chip Pad에서부터 Bonding Wire를 통한 Package Lead Frame까지를 의미한다. 여기서, Lead Frame 및 Bonding Wire에서 Inductance 및 작은 저항이 보이고, Chip Pad에서의 Capacitance, 그리고 Pad 부터 Ground까지의 Return Path에서 발생하는 저항이 보인다. 이들을 모두 합하면 L, R, C의 Series로 나타낼 수 있다. 본 논문에서는 이런 Chip Pin Parasitic을 추출 하기 위해서 TDR(Time Domain Reflectometer)과 NA(Network Analyzer)를 사용하였는데, TDR의 경우 PCB를 제작하여 Chip을 Board위에 붙인 후 Time Domain에서 측정 하였고 NA의 경우 Pico Probe를 이용하여 Chip pin에 직접 Probing해서 Smith Chart를 통하여 Extraction 값을 추출했다. 이 경우, NA를 이용한 측정이 좀 더 정확한 Parasitic 값을 추출할 수 있으리라 예상되겠지만, 실제로 Chip이 구동하기 위해서는 Board위에 있을 때의 상황도 고려해야 하기 때문에 TDR 추출 값과 NA 추출 값을 모두 비교하였다.

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A Study on the extraction of hydrologic-Model input parameter using GSIS (GSIS를 이용한 수문모형 입력매개변수 추출에 관한 연구)

  • Lee, Geung-Sang;Chae, Hyo-Seok;Park, Jeong-Nam;Cho, Gi-Sung
    • Journal of Korean Society for Geospatial Information Science
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    • v.8 no.2 s.16
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    • pp.11-22
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    • 2000
  • It needs to extract the accurate topological characteristics and hydrological parameters of watershed in order to manage water resource efficiently. But, these data are processed yet by manual wok and simple operation in hydrologic fields. In this paper, we presented algorithm that could extract topological characteristics and hydrological parameters over watershed using GSIS and it gives the saving of data processing tin and the confidency of data. We presented coupling method between GSIS and hydrologic model by using extracted parameters into the input parameter of HEC-HMS hydrologic model. The extraction procedure of topological characteristics and hydrological parameters is as below. First, watershed and stream are extracted by DEM and curve unmber is extracted throughout the overlay of landuse map and soil map. Also, we extracted surface parameters like the length of the longest flow path and the slope of the longest flow path by Grid computation into watershed and stream. And we gave the method that could extract hydrologic parameters like Muskingum K and sub-basin lag tin by executing computation into surface parameters and average Sn curve number being extracted.

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A Novel RGB Image Steganography Using Simulated Annealing and LCG via LSB

  • Bawaneh, Mohammed J.;Al-Shalabi, Emad Fawzi;Al-Hazaimeh, Obaida M.
    • International Journal of Computer Science & Network Security
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    • v.21 no.1
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    • pp.143-151
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    • 2021
  • The enormous prevalence of transferring official confidential digital documents via the Internet shows the urgent need to deliver confidential messages to the recipient without letting any unauthorized person to know contents of the secret messages or detect there existence . Several Steganography techniques such as the least significant Bit (LSB), Secure Cover Selection (SCS), Discrete Cosine Transform (DCT) and Palette Based (PB) were applied to prevent any intruder from analyzing and getting the secret transferred message. The utilized steganography methods should defiance the challenges of Steganalysis techniques in term of analysis and detection. This paper presents a novel and robust framework for color image steganography that combines Linear Congruential Generator (LCG), simulated annealing (SA), Cesar cryptography and LSB substitution method in one system in order to reduce the objection of Steganalysis and deliver data securely to their destination. SA with the support of LCG finds out the optimal minimum sniffing path inside a cover color image (RGB) then the confidential message will be encrypt and embedded within the RGB image path as a host medium by using Cesar and LSB procedures. Embedding and extraction processes of secret message require a common knowledge between sender and receiver; that knowledge are represented by SA initialization parameters, LCG seed, Cesar key agreement and secret message length. Steganalysis intruder will not understand or detect the secret message inside the host image without the correct knowledge about the manipulation process. The constructed system satisfies the main requirements of image steganography in term of robustness against confidential message extraction, high quality visual appearance, little mean square error (MSE) and high peak signal noise ratio (PSNR).

Location Generalization of Moving Objects for the Extraction of Significant Patterns (의미 패턴 추출을 위한 이동 객체의 위치 일반화)

  • Lee, Yon-Sik;Ko, Hyun
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.12 no.1
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    • pp.451-458
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    • 2011
  • In order to provide the optimal location based services such as the optimal moving path search or the scheduling pattern prediction, the extraction of significant moving pattern which is considered the temporal and spatial properties of the location-based historical data of the moving objects is essential. In this paper, for the extraction of significant moving pattern we propose the location generalization method which translates the location attributes of moving object into the spatial scope information based on $R^*$-tree for more efficient patterning the continuous changes of the location of moving objects and for indexing to the 2-dimensional spatial scope. The proposed method generates the moving sequences which is satisfied the constraints of the time interval between the spatial scopes using the generalized spatial data, and extracts the significant moving patterns using them. And it can be an efficient method for the temporal pattern mining or the analysis of moving transition of the moving objects to provide the optimal location based services.

Digital watermarking using binary phase hologram and optical interferometer (이진 위상 홀로그램과 광학적 간섭계를 이용한 디지털 워터마킹)

  • 김병열;서동환;조규보;신창목;김수중;김철수
    • Korean Journal of Optics and Photonics
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    • v.14 no.4
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    • pp.377-382
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    • 2003
  • We propose a new optical watermarking method, which can protect the copyright of digital data, using a binary phase hologram and a Mach-Zehnder interferometer. Using a simulated annealing algorithm, the binary phase hologram of the mark image to be hidden is designed. We obtained a watermarked image by linearly superposing the hologram, which is the watermark, in the original image. The extraction processing of the mark image from the watermarked image is achieved by placing the phase-modulated watermarked image on a LCD in one path and the phase-modulated original image on another LCD in the other path in the Mach-Zehnder interferometer. The mark image was obtained by inverse Fourier transforming the phase modulated interference intensity. We confirmed that the proposed method is robust for the cropped images through computer simulation, and we implemented it optically using LCDs which are phase modulation devices.

Switching Function Implementation based on Graph (그래프에 기초한 스위칭함수 구현)

  • Park, Chun-Myoung
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.9
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    • pp.1965-1970
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    • 2011
  • This paper proposes the method of switching function implementation using switching function extraction based on graph over finite fields. After we deduce the matrix equation from path number of directional graph, we propose the switching function circuit algorithm, also we propose the code assignment algorithm for nodes which is satisfied the directional graph characteristics with designed circuits. We can implement more optimal switching function compare with former algorithm, also we can design the switching function circuit which have any natural number path through the proposed switching function circuit implementation algorithms. Also the proposed switching function implementation using graph theory over finite fields have decrement number of input-output, circuit construction simplification, increment arithmetic speed and decrement cost etc.

An Implementation of Story Path Recommendation System of Interactive Drama Using PCA and NMF (PCA와 NMF를 이용한 대화식 드라마의 스토리 경로 추천 시스템 구현)

  • Lee, Yeon-Chang;Jang, Jae-Hee;Kim, Myung-Gwan
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.12 no.4
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    • pp.95-102
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    • 2012
  • Interactive drama is a story which requires user's free choice and participation. In this study, we grasp user's preference by making training data that utilize characters of interactive drama. Furthermore, we describe process of implementing systems which recommend new users path of stories that correspond with their preference. We used PCA and NMF to extract characteristic of preference. The success rate of recommending was 75% with PCA, while 62.5% with NMF.

Greedy Merging Method Based on Weighted Geometric Properties for User-Steered Mesh Segmentation (사용자 의도의 메쉬분할을 위한 기하적 속성 가중치 기반의 그리디 병합 방법)

  • Ha, Jong-Sung;Yoo, Kwan-Hee
    • The Journal of the Korea Contents Association
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    • v.7 no.6
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    • pp.52-59
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    • 2007
  • This paper presents a greedy method for user-steered mesh segmentation, which is based on the merging priority metric defined for representing the geometric properties of meaningful parts. The priority metric is a weighted function composed of five geometric parameters: distribution of Gaussian map, boundary path concavity, boundary path length, cardinality, and segmentation resolution. This scheme can be extended without any modification only by defining more geometric parameters and adding them. Our experimental results show that the shapes of segmented parts can be controlled by setting up the weight values of geometric parameters.

Digital Logic Extraction from Quantum-dot Cellular Automata Designs (Quantum-dot Cellular Automata 회로로부터 디지털 논리 추출)

  • Oh, Youn-Bo;Lee, Eun-Choul;Kim, Kyo-Sun
    • Proceedings of the KIEE Conference
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    • 2006.10c
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    • pp.139-141
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    • 2006
  • Quantum-dot Cellular Automata (QCA) is one of the most promising next generation nano-electronic devices which will inherit the throne of CMOS which is the domineering implementation technology of large scale low power digital systems. In late 1990s, the basic operations of the QCA cell were already demonstrated on a hardware implementation. Also, design tools and simulators were developed. Nevertheless, its design technology is not quite ready for ultra large scale designs. This paper proposes a new approach which enables the QCA designs to inherit the verification methodologies and tools of CMOS designs, as well. First, a set of disciplinary rules strictly restrict the cell arrangement not to deviate from the predefined structures but to guarantee the deterministic digital behaviors. After the gate and interconnect structures of the QCA design are identified, the signal integrity requirements including the input path balancing of majority gates, and the prevention of the noise amplification are checked. And then the digital logic is extracted and stored in the OpenAccess common engineering database which provides a connection to a large pool of CMOS design verification tools. Towards validating the proposed approach, we designed a 2-bit QCA adder. The digital logic is extracted, translated into the Verilog net list, and then simulated using a commercial software.

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