• Architectural research
• /
• v.1 no.1
• /
• pp.31-40
• /
• 1999

In this age of "Information", many people consider it a deterrent to information flow to provide a hierarchy with private rooms in a modern office layout. There are others, however, who insist that visual and acoustical privacy are more important than any other design factor in achieving higher productivity. The debate may never end, but the partitioned open plan, which is a new form of the vast open plan, has merits of each concept - open and closed layout. Consequently, office design has dramatically shifted to partitioned open planning, with shorter, temporary walls or partitions, originally intended for increasing privacy and diminishing hierarchy, yet still keeping flexibility in spatial organization. The introduction of low-level partitioned spaces in an office layout, however, produces a complicated lighting design problem. Obviously, accurately predicted daylighting performance data are needed not only for daylighting design but for artificial lighting system design. Scale models of 12 sets of unit partitioned spaces are constructed and extensive scale model measurements of both daylight and reflected sunlight have been performed within an artificial sky simulator. The prototype-building interior is modeled with different partition configurations, each of which is modeled using the different envelope geometry and exterior configurations, and then the variations in interior light levels are estimated. The result indicates that partitioned spaces employed in an open plan of modern offices still offer a large potential for daylighting and energy saving as well. Much of the savings may derive from the cumulative effect of reflected sunlight. Optimal design for building envelope geometry and exterior configuration promises additional savings.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.25 no.5
• /
• pp.572-579
• /
• 1988

In this paper, a system of automatic placement and routing for gate array layout design is proposed. In the placement stage, the circuit is partitioned and using the concept of min-cut slicing, and each partitioned module is placed, so that the routing density over the entire chip be uniformized and the total wiring length be minimized. In the global routing stage, the concept of the probabilistic routing density is introduced to unify the wiring congestions in each channel. In the detailed routing stage, the multi-terminal nets are partitioned into the two-terminal nets. The ordered channel graph is proposed which implies the vertical and the horizontal constranint graphs simultaneously. And using the ordered channel graph, the proposed routing algorithm assigns the signal nets to the tracks. Also the proposed placement and routing algorithms are implimented on IBM/PC-AT to construct PC-level gate array layout system.

• Journal of applied mathematics & informatics
• /
• v.20 no.1_2
• /
• pp.209-224
• /
• 2006

This paper presents an optimization model with performance constraints for two kinds of graph elements layout problem. The layout problem is partitioned into finite subproblems by using graph theory and group theory, such that each subproblem overcomes its on-off nature about optimal variable. Furthermore each subproblem is relaxed and the continuity about optimal variable doesn't change. We construct a min-max problem which is locally equivalent to the relaxed subproblem and develop the first order necessary and sufficient conditions for the relaxed subproblem by virtue of the min-max problem and the theories of convex analysis and nonsmooth optimization. The global optimal solution can be obtained through the first order optimality conditions.

• Journal of the Korea Society of Computer and Information
• /
• v.21 no.3
• /
• pp.1-8
• /
• 2016

The printed circuit board (PCB) can be used only 2 layers of front and back. Therefore, the wiring line segments are located in 2 layers without crossing each other. In this case, the line segment can be appear in both layers and this line segment is to resolve the crossing problem go through the via. The via minimization problem (VMP) has minimum number of via in layout design problem. The VMP is classified by NP-complete because of the polynomial time algorithm to solve the optimal solution has been unknown yet. This paper suggests polynomial time algorithm that can be solve the optimal solution of VMP. This algorithm transforms n-line segments into vertices, and p-crossing into edges of a graph. Then this graph is partitioned into 3-coloring sets of each vertex in each set independent each other. For 3-coloring sets $C_i$, (i=1,2,3), the $C_1$ is assigned to front F, $C_2$ is back B, and $C_3$ is B-F and connected with via. For the various experimental data, though this algorithm can be require O(np) polynomial time, we obtain the optimal solution for all of data.

• Journal of the Microelectronics and Packaging Society
• /
• v.20 no.4
• /
• pp.75-79
• /
• 2013

A power distribution network (PDN) is a network that provides connection between the voltage source supply and the power/ground terminals of a microprocessor chip. It consists of a voltage regulator module, a printed circuit board, a package substrate, a microprocessor chip as well as decoupling capacitors. For power integrity analysis, the board and package layouts have to be transformed into an electrical network of resistor, inductor and capacitor components which may be expressed using the S-parameters models. This modeling process generally takes from several hours up to a few days for a complete board or package layout. When the board and package layouts change, they need to be re-extracted and the S-parameters models also need to be re-generated for power integrity assessment. This not only consumes a lot of resources such as time and manpower, the task of PDN modeling is also tedious and mundane. In this paper, a block-based PDN modeling is proposed. Here, the board or package layout is partitioned into sub-blocks and each of them is modeled independently. In the event of a change in power rails routing, only the affected sub-blocks will be reextracted and re-modeled. Simulation results show that the proposed block-based PDN modeling not only can save at least 75% of processing time but it can, at the same time, keep the modeling accuracy on par with the traditional PDN modeling methodology.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.11
• /
• pp.128-139
• /
• 1996

In this paper, we propose an algorithm to solve the problem of placement of rectangular blocks whose sizes and shpaes are pre-determined. The proposed method solves the placement of many retangular blocks of different sizes and shapes in a hierarchical manner, so as to minimize the chip area. The placement problem is divided into several sub-problems: hierarchical partioning, hierarchical area/shape estimation, hierarchical pattern pacement, overlap removal, and module rotation. After the circuit is recursively partitioned to build a hierarchy tree, the necessary wiring area and module shpaes are estimated using the resutls of the partitioning and the pin information before the placement is performed. The placement templaes are defined to represent the relative positions of the modules. The area and the connectivity are optimized separately at each level of hierachy using the placement templates, so the minimization of chip area and wire length can be achieved in a short execution time. Experiments are made on the MCNC building block benchmark circuits and the results are compared with those of other published methods. The proposed technique is shown to produce good figures in tems of execution time and chip area.

• Journal of KIISE:Databases
• /
• v.31 no.6
• /
• pp.596-608
• /
• 2004

A lot of work has been done to reduce disk access time in I/O intensive systems, which store and handle massive amount of data, by distributing data across multiple disks and accessing them in parallel. Most of the previous work has focused on an efficient mapping from a grid cell to a disk number on the assumption that data space is regular grid-like partitioned. Although we can achieve good performance for low-dimensional data by grid-like partitioning, its performance becomes degenerate as grows the dimension of data even with a good disk allocation scheme. This comes from the fact that they partition entire data space equally regardless of distribution ratio of data objects. Most of the data in high-dimensional space exist around the surface of space. For that reason, we propose a new declustering algorithm based on the partitioning scheme which partition data space from the surface. With an unbalanced partitioning scheme, several experimental results show that we can remarkably reduce the number of data blocks touched by a query as grows the dimension of data and a query size. In this paper, we propose disk allocation schemes based on the layout of the resultant data blocks after partitioning. To show the performance of the proposed algorithm, we have performed several experiments with different dimensional data and for a wide range of number of disks. Our proposed disk allocation method gives a performance within 10 additive disk accesses compared with strictly optimal allocation scheme. We compared our algorithm with Kronecker sequence based declustering algorithm, which is reported to be the best among the grid partition and mapping function based declustering algorithms. We can improve declustering performance up to 14 times as grows dimension of data.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.3
• /
• pp.73-84
• /
• 2002

Fast and accurate new capacitance determination methodology for non-uniform complicated multi-layer VLSI interconnects is presented. Since a capacitance determination of intricate multi-layer interconnects using 3-dimensional field-solver is not practical, quasi-3-dimensional methodology is presented. Interconnects with discontinuity (i.e., bend structure and different spacing between lines, etc.) are partitioned. Then, each partial capacitance of divided parts is extracted by using 2-dimensional extraction methodology. For a multi-layer interconnects with shielding layer, the system can be simplified by investigating a distribution of charge in it. Thereby, quasi-3-dimensional capacitance for multi-layer interconnects can be determined by combining solid-ground based 2-dimensional capacitance and shielding effect which is independently determined with layout dimensions. This methodology for complicated multi-layer interconnects is more accurate and cost-efficient than conventional 3-dimensional methodology It is shown that the quasi-3-dimensional capacitance methodology has excellent agreement with 3-dimensional field- solver-based results within 5% error.

• Journal of The Korean Digital Architecture Interior Association
• /
• v.11 no.4
• /
• pp.5-11
• /
• 2011

The present study investigated the actual conditions of physical therapy rooms at long-term hospitals in Korea and conducted a comparative analysis to develop an efficient floor plan and facility improvement measures. 1. At hospitals surveyed, physical therapy services were used at a high frequency but they did not have enough space for rehab treatment and long paths of patient flow were found to make patient management inconvenient. Therefore, physical therapy units should be conveniently located both in terms of distance and direction so as to be accessible from patient rooms or wards. The space should be organized in a concentrated layout for efficiency of physical therapy, and floor planning for therapy units should ensure the best possible viewing angle to therapists. 2. With regard to the disease characteristics of patients, many physical therapy rooms were in difficult circumstances because of poor facilities, so they need to secure skilled personnel, supplement apparatuses and equipment and have rooms for functional recovery, hydrotherapy and operation treatment. In addition, each of the curtained or partitioned areas for treatment should be set up with consideration for the amount of space taken up by medical equipment. The area under each bed should be designed for patient convenience so that it can be used as storage space for patient's belongings and shoes. 3. Patients complained about the lack of physical therapy space, resting places or exercise areas and demanded the expansion of rehab programs and facilities. Physical therapy facilities need to be improved for patient privacy and effective natural ventilation. 4. At most of the long-term hospitals surveyed, physical therapy units were found to have small areas and treatment equipment and devices were insufficient compared to the number of patients. Therefore, it is required to secure more space (at least 138.24 sq. meters per 100 beds) and improve facilities for better physical therapy services.

• Journal of the Korean Solar Energy Society
• /
• v.22 no.3
• /
• pp.47-56
• /
• 2002

The office is an excellent candidate for implementing daylighting techniques because of the relatively high electric lighting power densities and long daytime use pattern. The quantity of light available for a space can be translated in term of the amount of energy savings through a process of a building energy simulation. To get significant energy savings in general illumination, the electric lighting system must be incorporated with a daylight - activated dimmer control. A prototype configuration of an office interior has been established and the integration between the building envelope and lighting and HVAC systems is evaluated based on computer modeling of a lighting control facility. First of all, an energy-efficient luminaire system is designed for both a totally open-plan office interior and a partitioned office. A lighting design and analysis program, Lumen-Micro 2000 predicts the optimal layout of a conventional fluorescent lighting fixture to meet the designed lighting level and calculates unit power density, which translates the demanded amount of electric lighting energy. A dimming control system integrated with the contribution of daylighting has been applied to the operating of the artificial lighting. Annual cooling load due to lighting and the projecting saving amount of cooling load due to daylighting under overcast diffuse sky are evaluated by a computer software, ENER-Win. In brief, the results from building energy simulation with measured daylight illumination levels and the performance of lighting control system indicate that daylighting can save over 70 percent of the required energy for general illumination in the perimeter zones through the year. A 25 % of electric energy for cooling may be saved by dimming and turning off the luminaires in the perimeter zones.