• Architectural research
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• 제1권1호
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• pp.31-40
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• 1999

In this age of "Information", many people consider it a deterrent to information flow to provide a hierarchy with private rooms in a modern office layout. There are others, however, who insist that visual and acoustical privacy are more important than any other design factor in achieving higher productivity. The debate may never end, but the partitioned open plan, which is a new form of the vast open plan, has merits of each concept - open and closed layout. Consequently, office design has dramatically shifted to partitioned open planning, with shorter, temporary walls or partitions, originally intended for increasing privacy and diminishing hierarchy, yet still keeping flexibility in spatial organization. The introduction of low-level partitioned spaces in an office layout, however, produces a complicated lighting design problem. Obviously, accurately predicted daylighting performance data are needed not only for daylighting design but for artificial lighting system design. Scale models of 12 sets of unit partitioned spaces are constructed and extensive scale model measurements of both daylight and reflected sunlight have been performed within an artificial sky simulator. The prototype-building interior is modeled with different partition configurations, each of which is modeled using the different envelope geometry and exterior configurations, and then the variations in interior light levels are estimated. The result indicates that partitioned spaces employed in an open plan of modern offices still offer a large potential for daylighting and energy saving as well. Much of the savings may derive from the cumulative effect of reflected sunlight. Optimal design for building envelope geometry and exterior configuration promises additional savings.

• 대한전자공학회논문지
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• 제25권5호
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• pp.572-579
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• 1988

In this paper, a system of automatic placement and routing for gate array layout design is proposed. In the placement stage, the circuit is partitioned and using the concept of min-cut slicing, and each partitioned module is placed, so that the routing density over the entire chip be uniformized and the total wiring length be minimized. In the global routing stage, the concept of the probabilistic routing density is introduced to unify the wiring congestions in each channel. In the detailed routing stage, the multi-terminal nets are partitioned into the two-terminal nets. The ordered channel graph is proposed which implies the vertical and the horizontal constranint graphs simultaneously. And using the ordered channel graph, the proposed routing algorithm assigns the signal nets to the tracks. Also the proposed placement and routing algorithms are implimented on IBM/PC-AT to construct PC-level gate array layout system.

• Journal of applied mathematics & informatics
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• 제20권1_2호
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• pp.209-224
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• 2006

This paper presents an optimization model with performance constraints for two kinds of graph elements layout problem. The layout problem is partitioned into finite subproblems by using graph theory and group theory, such that each subproblem overcomes its on-off nature about optimal variable. Furthermore each subproblem is relaxed and the continuity about optimal variable doesn't change. We construct a min-max problem which is locally equivalent to the relaxed subproblem and develop the first order necessary and sufficient conditions for the relaxed subproblem by virtue of the min-max problem and the theories of convex analysis and nonsmooth optimization. The global optimal solution can be obtained through the first order optimality conditions.

• 한국컴퓨터정보학회논문지
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• 제21권3호
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• pp.1-8
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• 2016

The printed circuit board (PCB) can be used only 2 layers of front and back. Therefore, the wiring line segments are located in 2 layers without crossing each other. In this case, the line segment can be appear in both layers and this line segment is to resolve the crossing problem go through the via. The via minimization problem (VMP) has minimum number of via in layout design problem. The VMP is classified by NP-complete because of the polynomial time algorithm to solve the optimal solution has been unknown yet. This paper suggests polynomial time algorithm that can be solve the optimal solution of VMP. This algorithm transforms n-line segments into vertices, and p-crossing into edges of a graph. Then this graph is partitioned into 3-coloring sets of each vertex in each set independent each other. For 3-coloring sets $C_i$, (i=1,2,3), the $C_1$ is assigned to front F, $C_2$ is back B, and $C_3$ is B-F and connected with via. For the various experimental data, though this algorithm can be require O(np) polynomial time, we obtain the optimal solution for all of data.

• 마이크로전자및패키징학회지
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• 제20권4호
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• pp.75-79
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• 2013

A power distribution network (PDN) is a network that provides connection between the voltage source supply and the power/ground terminals of a microprocessor chip. It consists of a voltage regulator module, a printed circuit board, a package substrate, a microprocessor chip as well as decoupling capacitors. For power integrity analysis, the board and package layouts have to be transformed into an electrical network of resistor, inductor and capacitor components which may be expressed using the S-parameters models. This modeling process generally takes from several hours up to a few days for a complete board or package layout. When the board and package layouts change, they need to be re-extracted and the S-parameters models also need to be re-generated for power integrity assessment. This not only consumes a lot of resources such as time and manpower, the task of PDN modeling is also tedious and mundane. In this paper, a block-based PDN modeling is proposed. Here, the board or package layout is partitioned into sub-blocks and each of them is modeled independently. In the event of a change in power rails routing, only the affected sub-blocks will be reextracted and re-modeled. Simulation results show that the proposed block-based PDN modeling not only can save at least 75% of processing time but it can, at the same time, keep the modeling accuracy on par with the traditional PDN modeling methodology.

• 전자공학회논문지A
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• 제33A권11호
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• pp.128-139
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• 1996

In this paper, we propose an algorithm to solve the problem of placement of rectangular blocks whose sizes and shpaes are pre-determined. The proposed method solves the placement of many retangular blocks of different sizes and shapes in a hierarchical manner, so as to minimize the chip area. The placement problem is divided into several sub-problems: hierarchical partioning, hierarchical area/shape estimation, hierarchical pattern pacement, overlap removal, and module rotation. After the circuit is recursively partitioned to build a hierarchy tree, the necessary wiring area and module shpaes are estimated using the resutls of the partitioning and the pin information before the placement is performed. The placement templaes are defined to represent the relative positions of the modules. The area and the connectivity are optimized separately at each level of hierachy using the placement templates, so the minimization of chip area and wire length can be achieved in a short execution time. Experiments are made on the MCNC building block benchmark circuits and the results are compared with those of other published methods. The proposed technique is shown to produce good figures in tems of execution time and chip area.

• 한국정보과학회논문지:데이타베이스
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• 제31권6호
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• pp.596-608
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• 2004

디스크 입출력 성능에 의해서 많은 영향을 받는 대용량의 데이타를 저장하고 처리하는 시스템에서 데이타를 다수의 병렬 디스크에 분산 시켜 저장한 후 질의 처리 시 디스크 접근 시간을 감소시키기 위한 노력들이 많이 행해졌다. 대부분의 이전 연구들은 데이타 공간이 정형의 그리드 형태로 분할되어 있다는 가정 하에 각 그리드 셀에 대해서 효과적으로 디스크 번호를 할당하는 알고리즘 연구에 치중하였다. 하지만, 그리드 형태의 분할은 저차원 데이타에 대해서는 효과적이지만 고차원 데이타에 대해서는 우수한 디스크 할당 알고리즘을 적용하더라도 디클러스터링에 의한 성능 향상을 이룰 수가 없다. 그 이유는 그리드 분할 방법은 데이타 분포 비율에 관계없이 전체 데이타 공간을 동일한 비율로 분할하기 때문이다. 고차원 데이타는 대부분 데이타 공간의 표면에 존재한다. 본 논문에서는 이와 같은 현상을 고려하여 데이타 표면으로부터 주기적으로 편중 분할하는 알고리즘을 이용한 새로운 디클러스터링 알고리즘을 제시한다. 다양한 실험 결과에 의하면 표면으로부터 주기적으로 편중 분할하는 방법은 차원이 증가할 수록, 또한 질의 크기가 증가할 수록 그리드 형태의 분할에 비해서 질의를 만족하는 데이타 블록의 수를 현저히 감소시킬 수 있다. 본 논문에서는 분할 결과 데이타 블록들의 배치(layout)를 이용한 디스크 번호 할당 알고리즘들을 제시하였다. 우리는 제시한 알고리즘의 성능을 보이기 위해서 다양한 차원과 디스크 수에 대해서 여러 가지 실험을 하였다. 본 연구에서 제시한 디스크 할당 알고리즘은 절대 최적의 디스크 할당 방법에 비해서 추가적인 디스크 접근 횟수가 10번을 넘지 않는다. 디클러스터링 알고리즘의 응답 시간에 대해서 그리드 분할에 대해서 가장 좋은 성능을 보이는 것으로 알려져 있는 Kronecker sequence을 이용한 디스크 할당 알고리즘과 비교하였으며 차원이 높아짐에 따라 최대 14배까지 성능이 향상된다.

• 대한전자공학회논문지SD
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• 제39권3호
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• pp.73-84
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• 2002

불규칙하고 복잡한 다층(multi-layer) VLSI 배선의 커패시턴스 추출을 위한 빠르고 정확한 새로운 방법을 개발하였다. 복잡한 다층 배선구조에서 3차원 field-solver를 사용하여 커패시턴스를 구하는 것은 현실적이지 않기 때문에 근사적 3차원 커패시턴스 추출 방법을 제안한다. 꺽이는 부분(bend)과 상이한 배선사이의 거리를 갖는 동일한 층내의 배선은 불연속한 부분과 만나는 곳을 분할하고 각각의 부분에 2차원 커패시턴스 추출 방법을 사용하여 커패시턴스를 추출하였다. 또한 차폐층(shielding layer)을 갖는 다층 배선 구조에서의 커패시턴스는 시스템 내의 전하의 분포를 조사함으로써 시스템을 간소화 시킨 후 평판 그라운드 기반 2차원 커패시턴스와 간단한 구조로부터 독립적으로 계산될 수 있는 차폐효과를 결합하여 근사적3차원 커패시턴스 추출 방법을 적용하였다. 불규칙한 다층 배선 구조에 대하여 설계된 레이아웃으로부터 해석적으로 구할 수 있는 변수와 평판 그라운드를 사용한 2차원 커패시턴스 추출 방법을 사용하므로 정확하면서도 신속하게 커패시턴스를 추출할 수 있어 일반적인 3차원 방법보다 비용 측면에서 훨씬 효과적이다. 제안된 근사적 3차원 방법을 통해 구한 커패시턴스는 3차원 field-solver를 기반으로 구한 커패시턴스와 오차율 5% 이내의 정확성을 나타낸다.

• 한국디지털건축인테리어학회논문집
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• 제11권4호
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• pp.5-11
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• 2011

The present study investigated the actual conditions of physical therapy rooms at long-term hospitals in Korea and conducted a comparative analysis to develop an efficient floor plan and facility improvement measures. 1. At hospitals surveyed, physical therapy services were used at a high frequency but they did not have enough space for rehab treatment and long paths of patient flow were found to make patient management inconvenient. Therefore, physical therapy units should be conveniently located both in terms of distance and direction so as to be accessible from patient rooms or wards. The space should be organized in a concentrated layout for efficiency of physical therapy, and floor planning for therapy units should ensure the best possible viewing angle to therapists. 2. With regard to the disease characteristics of patients, many physical therapy rooms were in difficult circumstances because of poor facilities, so they need to secure skilled personnel, supplement apparatuses and equipment and have rooms for functional recovery, hydrotherapy and operation treatment. In addition, each of the curtained or partitioned areas for treatment should be set up with consideration for the amount of space taken up by medical equipment. The area under each bed should be designed for patient convenience so that it can be used as storage space for patient's belongings and shoes. 3. Patients complained about the lack of physical therapy space, resting places or exercise areas and demanded the expansion of rehab programs and facilities. Physical therapy facilities need to be improved for patient privacy and effective natural ventilation. 4. At most of the long-term hospitals surveyed, physical therapy units were found to have small areas and treatment equipment and devices were insufficient compared to the number of patients. Therefore, it is required to secure more space (at least 138.24 sq. meters per 100 beds) and improve facilities for better physical therapy services.

• 한국태양에너지학회 논문집
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• 제22권3호
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• pp.47-56
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• 2002

The office is an excellent candidate for implementing daylighting techniques because of the relatively high electric lighting power densities and long daytime use pattern. The quantity of light available for a space can be translated in term of the amount of energy savings through a process of a building energy simulation. To get significant energy savings in general illumination, the electric lighting system must be incorporated with a daylight - activated dimmer control. A prototype configuration of an office interior has been established and the integration between the building envelope and lighting and HVAC systems is evaluated based on computer modeling of a lighting control facility. First of all, an energy-efficient luminaire system is designed for both a totally open-plan office interior and a partitioned office. A lighting design and analysis program, Lumen-Micro 2000 predicts the optimal layout of a conventional fluorescent lighting fixture to meet the designed lighting level and calculates unit power density, which translates the demanded amount of electric lighting energy. A dimming control system integrated with the contribution of daylighting has been applied to the operating of the artificial lighting. Annual cooling load due to lighting and the projecting saving amount of cooling load due to daylighting under overcast diffuse sky are evaluated by a computer software, ENER-Win. In brief, the results from building energy simulation with measured daylight illumination levels and the performance of lighting control system indicate that daylighting can save over 70 percent of the required energy for general illumination in the perimeter zones through the year. A 25 % of electric energy for cooling may be saved by dimming and turning off the luminaires in the perimeter zones.