• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.6
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• pp.1355-1362
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. Our LDPC decoder adopts a block-serial architecture based on min-sum algorithm and layered decoding scheme. A novel way to store check-node values and parity check matrix reduces the sizes of check-node memory and H-ROM. An efficient scheme for check-node memory addressing is used to achieve stall-free read/write operations. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.10 s.101
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• pp.965-972
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• 2005

In this paper, we first review LDPC codes in general and a belief propagation algorithm that works in logarithm domain. LDPC codes, which is chosen for second generation digital video broadcasting standard, are required a large number of computation due to large size of coded block and iteration. Therefore, we presented two kinds of low computational algorithm for LDPC codes. First, sequential decoding with partial group is proposed. It has same H/W complexity, and fewer number of iteration's are required at same performance in comparison with conventional decoder algerian. Secondly, early detection method for reducing the computational complexity is proposed. Using a confidence criterion, some bit nodes and check node edges are detected early on during decoding. Through the simulation, we knew that the iteration number are reduced by half using subset algorithm and computational complexity of early detected method is about $50\%$ offs in case of check node update, $99\%$ offs in case of check node update compared to conventional scheme.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2C
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• pp.148-154
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• 2010

In this paper, we first review LDPC codes in general and a belief propagation algorithm that works in logarithm domain. LDPC codes, which is chosen 802.11n for wireless local access network(WLAN) standard are required a large number of computation due to large size of coded block and iteration. Therefore, we presented three kinds of low computational algorithm for LDPC codes. First, sequential decoding with partial group is proposed. It has same H/W complexity, and fewer number of iteration's are required at same performance in comparison with conventional decoder algorithm. Secondly, we have apply early stop algorithm. This method is reduced number of unnecessary iteration. Third, early detection method for reducing the computational complexity is proposed. Using a confidence criterion, some bit nodes and check node edges are detected early on during decoding. Through the simulation, we knew that the iteration number are reduced by half using subset algorithm and early stop algorithm is reduced more than one iteration and computational complexity of early detected method is about 30% offs in case of check node update, 94% offs in case of check node update compared to conventional scheme.

• Women's Health Nursing
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• v.10 no.3
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• pp.226-234
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• 2004

Purpose: This study was to examine health status, reproductive health problems and the degree of prenatal management in working women. Method: The subjects were 902 married working women among 2,000 women selected by cluster sampling. The work area was classified to product factory, school, office, etc. After an Informed consent was obtained, participants were asked to fill out a self-administered questionnaire. The instruments included a questionnaire, parity check list, menstrual problems and gynecologic problem check list. Result: Many women have experienced menstrual cycle change during the past year. There was a significant difference in general health, menstrual regularity, reproductive health and prenatal management by occupation type. 40.6 percent of the subjects have gynecological problems such as menstrual cycle change, perineal inflammation, irregular vaginal bleeding, amenorrhea, ovarian/uterine disease, infertility, or abortion. Prenatal care was received in only 28.5% of the total subjects. In addition, 16.3% answered they had experienced low birth weight babies. Conclusion: We can conclude that working woman have changes in menstruation cycle and in reproductive health status. Therefore, we suggest that some occupational characteristics may affect subject's reproductive health, these should be clear and avoided as much as possible.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.10C
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• pp.935-941
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• 2007

In this paper, we suggest the power allocation method which enhances the performance in high SNR for LDPC codes. In this method, bit power is unequally allocated proportionally to the difference of the degree distributions of variable and check nodes of Tanner graph between practically used codes and the codes optimized by density evolution. Simulation is performed to the codes in IEEE 802.16e standards, and the results show that the proposed method works well in high SNR.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.5A
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• pp.402-406
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• 2005

A multiple input multiple output orthogonal frequency division multiplexing (MIMO-OFDM) system using low-density parity-check (LDPC) code and iterative decoding is presented. The iterative decoding is performed by combining the zero-forcing technique and LDPC decoding through the use of the 'turbo principle.' The proposed system is shown to be effective with high order modulation and outperforms the space frequency block code (SFBC) method with iterative decoding.

• Proceedings of the Korean Information Science Society Conference
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• 2005.11a
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• pp.535-537
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• 2005

디지털 신호 및 전송부호의 오류검출에는 예전부터 패리티 체크가 사용되어 왔다. 그러나 패리티 체크 기법은 구현 및 알고리즘이 단순, 간결한 우수성이 있지만 특정 데이터 비트의 경우 오류 검출이 불가능하다는 문제점을 가지고 있다. 이후 패리티 체크 기법은 해밍 코드 및 채널 오류 정정을 위한 LDPC 코드와 같은 다양한 오류검출 및 정정 알고리즘에 적용되어 발전되어 왔으며, 그 중 LDPC 코드의 bit-flipping 알고리즘에서는 패리티 기법을 반복적으로 적용하는 방식을 택하고 있다. 본 논문에서는 이러한 채널 오류 정정을 위한 LDPC의 bit-flipping 알고리즘을 이차원 코드에 적용하고, 이 때 bit-flipping 알고리즘이 가지고 있는 문제점을 보완할 수 있는 개선된 LDPC 코드를 제안한다.

• ETRI Journal
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• v.21 no.2
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• pp.9-21
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• 1999

In this paper, to enhance the performance of ${\pi}$/4-DQPSK (${\pi}$/4-differential quadrature phase shift keying), the scheme using nonredundant multiple error correction is proposed and investigated. This scheme for the differential detection of ${\pi}$/4-DQPSK uses the signal output which is delayed for more than two time slots as the parity check bit and applies it to nonredundant multiple error correction. The proposed system was used for studying the performance of ${\pi}$/4-DQPSK with Nonredundant Error Correction (NEC) in additive white Gaussian noise (AWGN) and Nakagami fade modeled mobile communication channel, and it was observed that the performance increased as the error correction capability increased.

• ETRI Journal
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• v.36 no.1
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• pp.171-174
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• 2014

In weighted bit-flipping-based algorithms for low-density parity-check (LDPC) codes, due to the existence of overconfident incorrectly received bits, the metric values of the corresponding bits will always be wrong in the decoding process. Since these bits cannot be flipped, decoding failure results. To solve this problem, an improved parallel weighted bit flipping algorithm is proposed. Specifically, a reliability-saturation strategy is adopted to increase the flipping probability of the overconfident incorrectly received bits. Simulation results show that the error floor of LDPC codes is greatly lowered.

• ETRI Journal
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• v.30 no.6
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• pp.799-806
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• 2008

In this paper, a new design for an error correcting code (ECC) is proposed. The design is aimed to build an ECC circuitry with minimal power consumption. The genetic algorithm equipped with the symbiotic mechanism is used to design a power-efficient ECC which provides single-error correction and double-error detection (SEC-DED). We formulate the selection of the parity check matrix into a collection of individual and specialized optimization problems and propose a symbiotic evolution method to search for an ECC with minimal power consumption. Finally, we conduct simulations to demonstrate the effectiveness of the proposed method.