• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.6C
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• pp.571-577
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• 2009

This paper proposes some new improved versions of node-wise VCRBP algorithm for low-density parity-check (LDPC) codes, called forced-convergence node-wise VCRBP algorithm and sign based node-wise VCRBP, both of which significantly reduce the decoding complexity and latency, with only negligible deterioration in error correcting performance.

• ETRI Journal
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• v.34 no.4
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• pp.629-632
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• 2012

This letter investigates the combination of the Chase-2 and sum-product (SP) algorithms for low-density parity-check (LDPC) codes. A simple modification of the tanh rule for check node update is given, which incorporates test error patterns (TEPs) used in the Chase algorithm into SP decoding of LDPC codes. Moreover, a simple yet effective approach is proposed to construct TEPs for dealing with decoding failures with low-weight syndromes. Simulation results show that the proposed algorithm is effective in improving both the waterfall and error floor performance of LDPC codes.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.10C
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• pp.942-949
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• 2007

In this paper, we propose a new rate-control scheme, called splining, to construct low-rate codes from high-rate codes by splitting rows of the parity-check matrices of LDPC codes, which can construct rate-compatible LDPC codes having good initial transmission performance. Good low-rate codes can be constructed by making the number of distinct check node degrees as small as possible after splitting. The proposed scheme achieves good cycle property, low decoding complexity, and fast convergence speed, especially compared to the puncturing. Especially, rate-compatible repeat accumulate-type LDPC (RA-Type LDPC) code is constructed using splitting, which covers the code rates from 1/3 to 4/5. Through simulation it is shown that this code outperforms other rate-compatible RA-Type LDPC codes for all rates and can be decoded conveniently and efficiently.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.3A
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• pp.179-187
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• 2012

In this paper, we propose an adaptive DFE (Decision Feedback Equalizer) based on LDPC (Low Density Parity Check) code for phase noise suppression and performance improvement. The proposed equalizer in this paper is applied for wireless repeater system. So as to meet ever increasing requirements on higher wireless access data rate and better quality of service (QoS), the wireless repeater system has been studied. The echo channel and RF impairments such as phase noise produce performance degradation. In order to remove echo channel and phase noise, we suggest a novel adaptive DFE equalizer based on LDPC code. The proposed equalizer helps to compensate RF impairments and improve the performance significantly better than used independently. In addition, proposed equalizer has less iteration number of LDPC code. So, the proposed equalizer system has low complexity.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2465-2473
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• 2011

This paper describes a circuit-level optimization of DFU(decoding function unit) for LDPC decoder which is used in wireless communication systems including WiMAX and WLAN. A new design of DFU based on sign-magnitude arithmetic instead of two's complement arithmetic is proposed, resulting in 18% reduction of gate count for 96 DFUs array used in mobile WiMAX LDPC decoder. A multi-mode LDPC decoder for mobile WiMAX standard is designed using the proposed DFU. The LDPC decoder synthesized using a 0.18-${\mu}m$ CMOS cell library with 50 MHz clock has 268,870 gates and 71,424 bits RAM, and it is verified by FPGA implementation.

• Journal of the Korea Society of Computer and Information
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• v.25 no.1
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• pp.29-36
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• 2020

Wear-leveling techniques and Error Correction Codes (ECCs) are essential for the improvement of the reliability and durability of flash memories. Low-Density Parity-Check (LDPC) codes have higher error correction capabilities than conventional ECCs and have been applied to various flash memory-based storage devices. Conventional wear-leveling schemes using only the number of Program/Erase (P/E) cycles are not enough to reflect the actual aging differences of flash memory components. This paper introduces an actual aging measurement scheme for flash memory wear-leveling using LDPC decoding information. Our analysis, using error-rates obtained from an flash memory module, shows that LDPC decoding information can represent the aging degree of each block. We also show the effectiveness of the wear-leveling based on the proposed scheme through wear-leveling simulation experiments.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.6 s.312
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• pp.110-116
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• 2006

In this paper, we implement a speech recognition system to support ubiquitous sensor network application services such as switch control, authentication, etc. using wireless audio sensors. The proposed system is consist of the wireless audio sensor, the speech recognition algorithm using psychoacoustic model and LDPC(low density parity check) for correcting errors. The proposed speech recognition system is inserted in a HOST PC to use the sensor energy effectively mil to improve the accuracy of speech recognition, a FEC(Forward Error Correction) system is used. Also, we optimized the simulation coefficient and test environment to effectively remove the wireless channel noises and correcting wireless channel errors. As a result, when the distance between sensor and the source of voice is less then 1.0m FAR and FRR are 0.126% and 7.5% respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2B
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• pp.325-333
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• 2010

Most communication systems including Wibro use quasi-cyclic LDPC codes composed of circulants. However, it is very difficult to design quasi-cyclic(QC) LDPC codes with optimal degree distribution satisfying conditions on layered decoding and girth due to the restriction of the size of its base matrix. In this paper, we propose a good solution by introducing superposition matrices to QC LDPC codes. We derive the conditions on checking girth of QC LDPC codes with superposition matrices, and propose new decoder to support layered decoding both for original QC LDPC codes and their modifications with superposition matrices. Simulation results show considerable improvements to convergence speed and error-correcting performance of proposed scheme which adopts QC LDPC codes with superposition matrices.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.2
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• pp.104-113
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• 2013

A high-throughput Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder architecture is proposed for 60GHz multi-gigabit wireless personal area network (WPAN) applications. Two novel techniques which can apply to our selected QC-LDPC code are proposed, including a four block-parallel layered decoding technique and fixed wire network. Two-stage pipelining and four block-parallel layered decoding techniques are used to improve the clock speed and decoding throughput. Also, the fixed wire network is proposed to simplify the switch network. A 672-bit, rate-1/2 QC-LDPC decoder architecture has been designed and implemented using 90-nm CMOS standard cell technology. Synthesis results show that the proposed QC-LDPC decoder requires a 794K gate and can operate at 290 MHz to achieve a data throughput of 3.9 Gbps with a maximum of 12 iterations, which meet the requirement of 60 GHz WPAN applications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.8C
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• pp.522-528
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• 2011

The iterative detection and decoding (IDD) has been shown to dramatically improve the bit error rate (BER) performance of the multiple-input multiple-output (MIMO) communication systems. However, these techniques require a high computational complexity since it is required to compute the soft decisions for each bit. In this paper, we show IDD comprised of sphere decoder with low-density parity check (LDPC) codes and present the tree search strategy, called a layer symbol search (LSS), to obtain soft decisions with a low computational complexity. In addition, an adaptive early termination is proposed to reduce the computational complexity during an iteration between an inner sphere decoder and an outer LDPC decoder. It is shown that the proposed approach can achieve the performance similar to an existing algorithm with 70% lower computational complexity compared to the conventional algorithms.