• Journal of Communications and Networks
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• v.15 no.1
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• pp.71-76
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• 2013

A new class of quantum low-density parity-check (LDPC) codes whose parity-check matrices are dual-containing matrices constructed based on lines of Euclidean geometries (EGs) is presented. The parity-check matrices of our quantum codes contain one and only one 4-cycle in every two rows and have better distance properties. However, the classical parity-check matrix constructed from EGs does not satisfy the condition of dual-containing. In some parameter conditions, parts of the rows in the matrix maybe have not any nonzero element in common. Notably, we propose four families of fascinating structure according to changes in all the parameters, and the parity-check matrices are adopted to satisfy the requirement of dual-containing. Series of matrix properties are proved. Construction methods of the parity-check matrices with dual-containing property are given. The simulation results show that the quantum LDPC codes constructed by this method perform very well over the depolarizing channel when decoded with iterative decoding based on the sum-product algorithm. Also, the quantum codes constructed in this paper outperform other quantum codes based on EGs.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.1
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• pp.128-136
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• 2008

In this paper, we propose a new cache structure for effective error correction of soft error. We added check bit and SEEB(soft error evaluation block) to evaluate the status of cache line. The SEEB stores result of parity check into the two-bit shit register and set the check bit to '1' when parity check fails twice in the same cache line. In this case the line where parity check fails twice is treated as a vulnerable to soft error. When the data is filled into the cache, the new replacement algorithm is suggested that it can only use the valid block determined by SEEB. This structure prohibits the vulnerable line from being used and contributes to efficient use of cache by the reuse of line where parity check fails only once can be reused. We tried to minimize the side effect of the proposed cache and the experimental results, using SPEC2000 benchmark, showed 3% degradation in hit rate, 15% timing overhead because of parity logic and 2.7% area overhead. But it can be considered as trivial for SEEB because almost tolerant design inevitably adopt this parity method even if there are some overhead. And if only parity logic is used then it can have $5%{\sim}10%$ advantage than ECC logic. By using this proposed cache, the system will be protected from the threat of soft error in cache and the hit rate can be maintained to the level without soft error in the cache.

• Journal of Communications and Networks
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• v.11 no.5
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• pp.455-463
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• 2009

We consider the challenges of finding good puncturing patterns for rate-compatible low-density parity-check code (LDPC) codes over additive white Gaussian noise (AWGN) channels. Puncturing is a scheme to obtain a series of higher rate codes from a lower rate mother code. It is widely used in channel coding but it causes performance is lost compared to non-punctured LDPC codes at the same rate. Previous work, considered the role of survived check nodes in puncturing patterns. Limitations, such as single survived check node assumption and simulation-based verification, were examined. This paper analyzes the performance according to the role of multiple survived check nodes and multiple dead check nodes. Based on these analyses, we propose new algorithm to find a good puncturing pattern for LDPC codes over AWGN channels.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.9
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• pp.1728-1730
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• 2015

In this letter, a parity check based iterative IC scheme is proposed for LDPC coded MIMO systems. After the decoding procedures in each iteration of the proposed scheme, each decoded codeword is utilized for the IC procedures only when the ratio of the check nodes satisfying the parity check equations to the total number of check nodes is not smaller than the pre-defined threshold value. Simulation results verify that the proposed scheme can achieve an improved BLER at the high SNR region compared to the conventional iterative IC scheme.

• ETRI Journal
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• v.27 no.5
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• pp.557-562
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• 2005

Low-density parity-check (LDPC) codes have recently emerged due to their excellent performance. However, the parity check (H) matrices of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix which is efficient in hardware implementation of both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the proposed methods, the implementation of encoders can become practical while keeping the hardware complexity of the partly parallel decoder structures. An encoder and a decoder are designed using Verilog-HDL and are synthesized using a $0.35 {\mu}m$ CMOS standard cell library.

• ETRI Journal
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• v.29 no.3
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• pp.381-389
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• 2007

In this paper we propose a graph-theoretic method based on linear congruence for constructing low-density parity check (LDPC) codes. In this method, we design a connection graph with three kinds of special paths to ensure that the Tanner graph of the parity check matrix mapped from the connection graph is without short cycles. The new construction method results in a class of (3, ${\rho}$)-regular quasi-cyclic LDPC codes with a girth of 12. Based on the structure of the parity check matrix, the lower bound on the minimum distance of the codes is found. The simulation studies of several proposed LDPC codes demonstrate powerful bit-error-rate performance with iterative decoding in additive white Gaussian noise channels.

• Journal of Communications and Networks
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• v.13 no.3
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• pp.205-210
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• 2011

This paper presents an approach to the construction of multiple-rate quasi-cyclic low-density parity-check (LDPC) codes. Parity-check matrices of the proposed codes consist of $q{\times}q$ square submatrices. The block rows and block columns of the parity-check matrix correspond to the hyperplanes (${\mu}$-fiats) and points in Euclidean geometries, respectively. By decomposing the ${\mu}$-fiats, we obtain LDPC codes of different code rates and a constant code length. The code performance is investigated in term of the bit error rate and compared with those of LDPC codes given in IEEE standards. Simulation results show that our codes perform very well and have low error floors over the additive white Gaussian noise channel.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.7 s.349
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• pp.50-57
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• 2006

Low-density parity-check (LDPC) codes are recently emerged due to its excellent performance. However, the parity check (H) matrices of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix which is efficient in hardware implementation of both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the proposed methods, the implementation of encoders can become practical while keeping the hardware complexity of the partly parallel decoder structures. An encoder and a decoder are designed using Verilog-HDL and compared with the previous results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.1A
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• pp.34-42
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• 2012

Low density parity check (LDPC) code is widely used, since it shows superior performance close to Shannon limit and its decoding complexity is lower than turbo code. Recently, it is used as a channel code to decode Wyner-Ziv frames in distributed video coding (DVC) system. In this paper, we propose an efficient method to design the parity check matrix H of LDPC codes. In order to apply LDPC code to DVC system, the LDPC code should have rate compatibility. Thus, we also propose a method to merge check nodes of LDPC code to attain the rate compatibility. LDPC code is designed using ACE algorithm and check nodes are merged for a given code rate to maximize the error correction capability. The performance of the designed LDPC code is analyzed extensively by computer simulations.

• ETRI Journal
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• v.46 no.3
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• pp.485-500
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• 2024

A hardware architecture is presented to decode (N, K) polar codes based on a low-density parity-check code-like decoding method. By applying suitable pruning techniques to the dense graph of the polar code, the decoder architectures are optimized using fewer check nodes (CN) and variable nodes (VN). Pipelining is introduced in the CN and VN architectures, reducing the critical path delay. Latency is reduced further by a fully parallelized, single-stage architecture compared with the log N stages in the conventional belief propagation (BP) decoder. The designed decoder for short-to-intermediate code lengths was implemented using the Virtex-7 field-programmable gate array (FPGA). It achieved a throughput of 2.44 Gbps, which is four times and 1.4 times higher than those of the fast-simplified successive cancellation and combinational decoders, respectively. The proposed decoder for the (1024, 512) polar code yielded a negligible bit error rate of 10^-4 at 2.7 E_b/N_o (dB). It converged faster than the BP decoding scheme on a dense parity-check matrix. Moreover, the proposed decoder is also implemented using the Xilinx ultra-scale FPGA and verified with the fifth generation new radio physical downlink control channel specification. The superior error-correcting performance and better hardware efficiency makes our decoder a suitable alternative to the successive cancellation list decoders used in 5G wireless communication.